[PATCH] D138529: [AVR] Optimize constant 32-bit shifts

Ben Shi via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Dec 7 03:07:25 PST 2022


benshi001 added inline comments.


================
Comment at: llvm/lib/Target/AVR/AVRISelLowering.cpp:2008
+  }
+
+  // Shift by four bits, using a complicated swap/eor/andi/eor sequence.
----------------
So here should be an `assert((ShiftAmt > -8 && ShiftAmt < 8) && "Unexpect shift amount");`


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138529/new/

https://reviews.llvm.org/D138529



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