[PATCH] D138529: [AVR] Optimize constant 32-bit shifts

[Ben Shi via Phabricator via llvm-commits]

benshi001 added inline comments.


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Comment at: llvm/lib/Target/AVR/AVRISelLowering.cpp:2004
+    // Continue shifts with the leftover registers.
+    Regs = Regs.slice(1, Regs.size() - 1);
+
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I am a bit confused about here. With `Regs = Regs.slice(1, Regs.size() - 1);`, so the 0 index element is dropped, and only 3 elements left in `Regs` ?


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  https://reviews.llvm.org/D138529/new/

https://reviews.llvm.org/D138529