[PATCH] D139411: [AAch64] Optimize muls with operands having enough zero bits.
Dave Green via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 6 04:05:33 PST 2022
dmgreen added a comment.
Can you add a couple of testcases for the edgecases too. Something like `%and = and i64 %ext64, 8589934591` and `%and = and i64 %ext64, 2147483647`
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rG LLVM Github Monorepo
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https://reviews.llvm.org/D139411/new/
https://reviews.llvm.org/D139411
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