[PATCH] D139411: [AAch64] Optimize muls with operands having enough zero bits.
Biplob Mishra via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 6 05:08:19 PST 2022
bipmis updated this revision to Diff 480436.
bipmis added a comment.
Corner case tests added. Rebase with tests committed.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D139411/new/
https://reviews.llvm.org/D139411
Files:
llvm/lib/Target/AArch64/AArch64InstrInfo.td
llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll
llvm/test/CodeGen/AArch64/aarch64-mull-masks.ll
llvm/test/CodeGen/AArch64/addcarry-crash.ll
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D139411.480436.patch
Type: text/x-patch
Size: 11110 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20221206/758a9008/attachment.bin>
More information about the llvm-commits
mailing list