[PATCH] D137504: [PowerPC] Implement 64-bit ELFv2 Calling Convention in TableGen (for integers/floats/vectors in registers)

[Amy Kwan via Phabricator via llvm-commits]

amyk added inline comments.


================
Comment at: llvm/lib/Target/PowerPC/PPCCallingConv.cpp:24
 
+// This function handles the shadowing the GPRs for fp and vector types.
+inline bool CC_PPC64_ELF_Shadow_GPR_Regs(unsigned &ValNo, MVT &ValVT,
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stefanp wrote:
> nit:
> ```
> This function handles the shadowing the GPRs for fp and vector types.
> ```
> to:
> ```
> This function handles the shadowing of GPRs for fp and vector types.
> ```
Good catch, I will update this. 


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Comment at: llvm/lib/Target/PowerPC/PPCCallingConv.cpp:43
+  if (LocVT == MVT::f32 || LocVT == MVT::f64) {
+    int SizeInDWord = (LocVT.getSizeInBits() + 63) / 64;
+    unsigned GPRIndToShadow = FirstUnallocGPR + SizeInDWord;
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stefanp wrote:
> I'm not sure you need this computation at all.
> `LocVT.getSizeInBits()`  is either 32 or 64 because we know that LocVT is either `MVT::f32` or `MVT::f64`.
> However, in that case 
> ```
> f32
> SizeInDWord = (32 + 63) / 64 = 1
> f64
> SizeInDWord = (64 + 63) / 64 = 1
> ```
> Both are integer divisions which just discard the decimal part. So, it looks to always be 1 in this situation. 
That's actually a good point. Thanks Stefan. 


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  https://reviews.llvm.org/D137504/new/

https://reviews.llvm.org/D137504