[PATCH] D137504: [PowerPC] Implement 64-bit ELFv2 Calling Convention in TableGen (for integers/floats/vectors in registers)

[Stefan Pintilie via Phabricator via llvm-commits]

stefanp added a comment.

Silly question:
Can we now get rid of `CC_PPC64_ELF_FIS` completely?



================
Comment at: llvm/lib/Target/PowerPC/PPCCallingConv.cpp:24
 
+// This function handles the shadowing the GPRs for fp and vector types.
+inline bool CC_PPC64_ELF_Shadow_GPR_Regs(unsigned &ValNo, MVT &ValVT,
----------------
nit:
```
This function handles the shadowing the GPRs for fp and vector types.
```
to:
```
This function handles the shadowing of GPRs for fp and vector types.
```


================
Comment at: llvm/lib/Target/PowerPC/PPCCallingConv.cpp:43
+  if (LocVT == MVT::f32 || LocVT == MVT::f64) {
+    int SizeInDWord = (LocVT.getSizeInBits() + 63) / 64;
+    unsigned GPRIndToShadow = FirstUnallocGPR + SizeInDWord;
----------------
I'm not sure you need this computation at all.
`LocVT.getSizeInBits()`  is either 32 or 64 because we know that LocVT is either `MVT::f32` or `MVT::f64`.
However, in that case 
```
f32
SizeInDWord = (32 + 63) / 64 = 1
f64
SizeInDWord = (64 + 63) / 64 = 1
```
Both are integer divisions which just discard the decimal part. So, it looks to always be 1 in this situation. 


================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:18213
   default:
-    return CC_PPC64_ELF_FIS;
+    return CC_PPC64_ELF;
   }
----------------
Does this also need to be changed in PPCFastISel? 


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D137504/new/

https://reviews.llvm.org/D137504