[PATCH] D137504: [PowerPC] Implement 64-bit ELFv2 Calling Convention in TableGen (for integers/floats/vectors in registers)

[Amy Kwan via Phabricator via llvm-commits]

amyk updated this revision to Diff 479799.
amyk added a comment.

Address review comments:

- Update comments.
- Clean up section involving shadowing GPRs for float/double.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D137504/new/

https://reviews.llvm.org/D137504

Files:
  llvm/lib/Target/PowerPC/PPCCallingConv.cpp
  llvm/lib/Target/PowerPC/PPCCallingConv.h
  llvm/lib/Target/PowerPC/PPCCallingConv.td
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/GlobalISel/irtranslator-args-lowering-fp128.ll
  llvm/test/CodeGen/PowerPC/GlobalISel/irtranslator-args-lowering-mixed-types.ll
  llvm/test/CodeGen/PowerPC/GlobalISel/irtranslator-args-lowering-scalar.ll
  llvm/test/CodeGen/PowerPC/GlobalISel/irtranslator-args-lowering-vectors.ll
  llvm/test/CodeGen/PowerPC/GlobalISel/irtranslator-args-lowering.ll

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