[PATCH] D129735: [RISCV] Add new pass to transform undef to pesudo for vector values.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/rvv/subregister-undef-early-clobber-vrm4.mir:118
+    %1:vrm4 = IMPLICIT_DEF
+    %5:vrm2 = PseudoRVVInitUndefM2
+    %6:vrm4 = INSERT_SUBREG %1:vrm4, %5, %subreg.sub_vrm2_0
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Why is there an PseudoRVVInitUnde pseudo in the IR before the pass runs?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129735/new/

https://reviews.llvm.org/D129735