[PATCH] D129735: [RISCV] Add new pass to transform undef to pesudo for vector values.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp:1
+//===- RISCVInitUndef.cpp - Initialize undef vector value to pesudo -------===//
+//
----------------
pesudo -> pseudo


================
Comment at: llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp:10
+// This file implements a function pass that initializes undef vector value to
+// temporary pesudo instruction and remove it in expandpesudo pass to prevent
+// register allocation resulting in a constraint violated result for vector
----------------
"pesudo" -> "pseudo"  in two places


================
Comment at: llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp:18
+// allocator allocated same or overlapped if the input register is undef value,
+// so convert IMPLICIT_DEF to temporary pesudo instruction and remove it latter
+// could prevent that happen, it's not best way to resolve this, and it might
----------------
pesudo -> pseudo


================
Comment at: llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp:18
+// allocator allocated same or overlapped if the input register is undef value,
+// so convert IMPLICIT_DEF to temporary pesudo instruction and remove it latter
+// could prevent that happen, it's not best way to resolve this, and it might
----------------
craig.topper wrote:
> pesudo -> pseudo
latter -> later


================
Comment at: llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp:245
+
+// If Sub-register liveness is enable, then we only need to PesudoInit undef
+// sub-register instead of whole regitser. Otherwise, it will generate redundant
----------------
Pesudo -> Pseudo


================
Comment at: llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp:246
+// If Sub-register liveness is enable, then we only need to PesudoInit undef
+// sub-register instead of whole regitser. Otherwise, it will generate redundant
+// COPY. For this purpose, there are some steps to meet this requirement.
----------------
regitser -> register


================
Comment at: llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp:288
+      if (SRDef->getOpcode() == TargetOpcode::PHI)
+        CandidataLaneMask = CandidataLaneMask & ~PHINodeLaneBitRecord[SRDef];
+
----------------
Candidata -> Candidate?


================
Comment at: llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll:28
 ; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT:    vloxseg2ei32.v v8, (a0), v8
+; CHECK-NEXT:    vloxseg2ei32.v v16, (a0), v8
 ; CHECK-NEXT:    csrr a0, vlenb
----------------
Are we treating insert_subreg for segment load tuples the same as inserting a small LMUL into a wider LMUL?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129735/new/

https://reviews.llvm.org/D129735