[PATCH] D129735: [RISCV] Add new pass to transform undef to pesudo for vector values.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp:73
+                         MachineBasicBlock::iterator &Inst);
+  bool isVectorRegClass(const Register &R);
+  bool handleSubRegister(MachineBasicBlock &MBB,
----------------
You can pass Register by value


================
Comment at: llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp:105
+  } while (Super);
+  // If we don't encounter VR then return origin one.
+  return RC;
----------------
origin -> original


================
Comment at: llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp:110
+bool RISCVInitUndef::isVectorRegClass(const Register &R) {
+  unsigned RegClassID = getVRLargestSuperClass(MRI->getRegClass(R))->getID();
+  switch (RegClassID) {
----------------
Can't we do something like

```
VRRegClass.hasSubClassEq(MRI->getRegClass(R)) ||
VRM2RegClass.hasSubClassEq(MRI->getRegClass(R)) ||
VRM4RegClass.hasSubClassEq(MRI->getRegClass(R)) ||
VRM8RegClass.hasSubClassEq(MRI->getRegClass(R))
```

why do we need to use getVRLargestSuperClass?



Repository:
  rG LLVM Github Monorepo

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https://reviews.llvm.org/D129735