[PATCH] D138812: [AArch64] lower abs intrinsic to new ABS instruction in SelDag

[Dave Green via Phabricator via llvm-commits]

dmgreen added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64InstrFormats.td:7274
+  let Predicates = [pred] in {
   def : Pat<(i64 (OpNode (i64 FPR64:$Rn))),
             (!cast<Instruction>(NAME # "v1i64") FPR64:$Rn)>;
----------------
I'm not sure this pattern will be used for anything. It can probably just be removed without modifying any tests.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138812/new/

https://reviews.llvm.org/D138812