[PATCH] D138812: [AArch64] lower abs intrinsic to new ABS instruction in SelDag

[Sam Elliott via Phabricator via llvm-commits]

lenary added a comment.

Tests LGTM. One slight cleanup would be neater.



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Comment at: llvm/lib/Target/AArch64/AArch64InstrFormats.td:7269
+                          SDPatternOperator OpNode = null_frag,
+                          Predicate pred = IsTrue> {
   def v1i64       : BaseSIMDTwoScalar<U, 0b11, 0b00, opc, FPR64, FPR64, asm,
----------------
This would be equivalent and neater, and allow multiple predicates.


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Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.td:236
                        AssemblerPredicateWithAll<(all_of FeatureMOPS), "mops">;
+def IsTrue           : Predicate<"true">;
 def IsLE             : Predicate<"Subtarget->isLittleEndian()">;
----------------
Not needed if you use the list of predicates.


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Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.td:5040
 
-defm ABS    : SIMDTwoScalarD<    0, 0b01011, "abs", abs>;
+defm ABS    : SIMDTwoScalarD<    0, 0b01011, "abs", abs, HasNoCSSC>;
 defm CMEQ   : SIMDCmpTwoScalarD< 0, 0b01001, "cmeq", AArch64cmeqz>;
----------------
This would be the relevant update here to match the suggested edit above.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138812/new/

https://reviews.llvm.org/D138812