[PATCH] D138813: [AArch64] implement GPR (U/S)(MIN/MAX) instruction SDag support

[Kyrill Tkachov via Phabricator via llvm-commits]

ktkachov added inline comments.


================
Comment at: llvm/test/CodeGen/AArch64/min-max.ll:142-149
 ;
+; CHECK-ISEL-CSSC-LABEL: smax32i8:
+; CHECK-ISEL-CSSC:       // %bb.0:
+; CHECK-ISEL-CSSC-NEXT:    smax v1.16b, v1.16b, v3.16b
+; CHECK-ISEL-CSSC-NEXT:    smax v0.16b, v0.16b, v2.16b
+; CHECK-ISEL-CSSC-NEXT:    stp q0, q1, [x0]
+; CHECK-ISEL-CSSC-NEXT:    ret
----------------
I'm not very familiar with tests in LLVM, but you shouldn't need CSSC for the vector smax/smin. CSSC only adds GP-register variants.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138813/new/

https://reviews.llvm.org/D138813