[PATCH] D138813: [AArch64] implement GPR (U/S)(MIN/MAX) instruction SDag support

[Ties Stuij via Phabricator via llvm-commits]

stuij added inline comments.


================
Comment at: llvm/test/CodeGen/AArch64/min-max.ll:142-149
 ;
+; CHECK-ISEL-CSSC-LABEL: smax32i8:
+; CHECK-ISEL-CSSC:       // %bb.0:
+; CHECK-ISEL-CSSC-NEXT:    smax v1.16b, v1.16b, v3.16b
+; CHECK-ISEL-CSSC-NEXT:    smax v0.16b, v0.16b, v2.16b
+; CHECK-ISEL-CSSC-NEXT:    stp q0, q1, [x0]
+; CHECK-ISEL-CSSC-NEXT:    ret
----------------
ktkachov wrote:
> I'm not very familiar with tests in LLVM, but you shouldn't need CSSC for the vector smax/smin. CSSC only adds GP-register variants.
Thanks for the comment :)
To be verbose: the CHECK-ISEL-CSSC prefix corresponds to a test run of this file with a particular configuration. This file also includes tests for the vector variants of the instructions and tests those with other configurations (specified by te RUN lines at the top of the file). What we're testing here is that the scalar codegen doesn't interfere with the vector codegen.


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https://reviews.llvm.org/D138813