[PATCH] D138639: [X86] Add In64BitMode for MOVSX64/MOVZX64 instructions

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D138639#3950081 <https://reviews.llvm.org/D138639#3950081>, @HaohaiWen wrote:

>> Isn't X86::CVTSD2SI64rm the CodeGenOnly instruction?
>
> Yes, CVTSD2SI64rm isCodeGenOnly and CVTSD2SI64rm_Int is not.
> I'm trying to auto gen asm enumeration for each encodable instructions. This relies on predicates to indicate the mode {16bit, 32bit, 64bit}.

We’ve been assuming the assembler would never parse a GR64 register name outside of 64-bit mode which is why the predicates were omitted.


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