[PATCH] D138639: [X86] Add In64BitMode for MOVSX64/MOVZX64 instructions
Haohai, Wen via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Nov 24 16:52:24 PST 2022
HaohaiWen added a comment.
> Isn't X86::CVTSD2SI64rm the CodeGenOnly instruction?
Yes, CVTSD2SI64rm isCodeGenOnly and CVTSD2SI64rm_Int is not.
I'm trying to auto gen asm enumeration for each encodable instructions. This relies on predicates to indicate the mode {16bit, 32bit, 64bit}.
Repository:
rG LLVM Github Monorepo
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https://reviews.llvm.org/D138639/new/
https://reviews.llvm.org/D138639
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