[PATCH] D138639: [X86] Add In64BitMode for MOVSX64/MOVZX64 instructions

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D138639#3948601 <https://reviews.llvm.org/D138639#3948601>, @HaohaiWen wrote:

>> Are you seeing a functional issue that this fixes?
>
> I'm fixing a AlderlakeP schedmodel issue: https://github.com/llvm/llvm-project/issues/58792.
> To fix it, I need to use AsmMatcherEmitter to match CodeGenOnly but encodable instructions like CVTSD2SI64rm_Int.

I'm not following. It's already not a CodeGenOnly instruction. I see this in the asm matcher table

  { 2010 /* cvtsd2si */, X86::CVTSD2SI64rm_Int, Convert__Reg1_1__Mem645_0, AMFBS_None, { MCK_Mem64, MCK_GR64 }, }

Isn't X86::CVTSD2SI64rm the CodeGenOnly instruction?


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https://reviews.llvm.org/D138639