[PATCH] D138570: [AArch64] Add patterns for SVE predicated add/sub and mov combine

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added a comment.

In D138570#3949132 <https://reviews.llvm.org/D138570#3949132>, @dmgreen wrote:

> Do you think that is as important in this case?

It's not super important, it's just something that we made a conscious choice to avoid after hitting issues with our original downstream implementation. I'm not too bothered about the CSE side of things, it's more to keep the patterns maintainable. For example, if SVE gains a predicated add/sub imm instruction then you start needing to duplicate these patterns.  Of course this can be refactored when such value can be gained so it's not a demand just a suggestion.  I'd have a stronger view if `AArch64add_m1` existed as an ISD node but it doesn't so I'm happy either way.


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