[PATCH] D138570: [AArch64] Add patterns for SVE predicated add/sub and mov combine

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

I think the H/S/D should be 255 too, according to https://godbolt.org/z/zcYcdGjfh. It looks like it's a 8bit encoding, that gets treated as a signed value so 255 becomes -1.

> For SVE we've tried to minimise the number of patterns that emit multiple instructions so I'm wondering if instead this can be a post legalisation DAG combine that emits int_aarch64_sve_add/sub intrinsics?

Do you think that is as important in this case? It is a good rule if the instructions could be combined into others (we try to use that rule in general for all of Arm/AArch64), but in this case the DUP_ZI_B are leaf nodes. They should all be CSE'd and remat trivially by the rest of the backend, and won't be combined into anything else.


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https://reviews.llvm.org/D138570