[PATCH] D138570: [AArch64] Add patterns for SVE predicated add/sub and mov combine

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added a comment.

For SVE we've tried to minimise the number of patterns that emit multiple instructions so I'm wondering if instead this can be a post legalisation DAG combine that emits int_aarch64_sve_add/sub intrinsics?



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Comment at: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td:3136
 
+let Predicates = [HasSVE] in {
+  def : Pat<(nxv16i8 (add ZPR:$op, (zext (nxv16i1 PPR:$pred)))),
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This likely wants to be HasSVEorSME.


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Comment at: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td:3137
+let Predicates = [HasSVE] in {
+  def : Pat<(nxv16i8 (add ZPR:$op, (zext (nxv16i1 PPR:$pred)))),
+            (ADD_ZPmZ_B PPR:$pred, ZPR:$op, (DUP_ZI_B 1, 0))>;
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Given the previous work that did land, do these patterns ever match? I mean we shouldn't have any `zext` of predicate vectors by this point should we? Or do you plan to revert that patch once this lands.


Repository:
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  https://reviews.llvm.org/D138570/new/

https://reviews.llvm.org/D138570