[PATCH] D138424: [TargetLowering][AArch64] Teach DemandedBits about VSCALE and SVE CNTx

[Benjamin Maxwell via Phabricator via llvm-commits]

benmxwl-arm added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1140
+      return false;
+    int64_t VScaleResultUpperbound = *MaxVScale;
+    if (auto *MulImm = dyn_cast<ConstantSDNode>(Op.getOperand(0))) {
----------------
dmgreen wrote:
> Could this just use construct known bits of both sides and use KnownBits::mul? It might be able to get value out of the low bits then too.
Please correct me if I've made a silly mistake here, but it does not seem to be exactly KnownBits::mul:

```
    Optional<unsigned> MaxVScale = Attr.getVScaleRangeMax();
    if (!MaxVScale.has_value())
      return false;
    if (auto *MulImm = dyn_cast<ConstantSDNode>(Op.getOperand(0))) {
      unsigned RequiredBits = Log2_64(*MaxVScale) + 1;
      if (RequiredBits >= BitWidth)
        return false;
      Known.Zero.setHighBits(BitWidth - RequiredBits);
      Known = KnownBits::mul(Known, KnownBits::makeConstant(MulImm->getAPIntValue()));
    }
    return false;
```

If the MaxVScale is 16 (5 bits)

The known zero bits are everything above Log2(16 * Mul) + 1.
The above snippet seems to end up with Log2((2^5 - 1) * Mul) + 1 (which is off by 1 bit)

Also it seems that KnowBits::mul can't handle negative multipliers and always reports no known bits in that case.




Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138424/new/

https://reviews.llvm.org/D138424