[PATCH] D138424: [TargetLowering][AArch64] Teach DemandedBits about VSCALE and SVE CNTx

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

This may be better as two separate patches, one for the vscale and one for the cnt's



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Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1140
+      return false;
+    int64_t VScaleResultUpperbound = *MaxVScale;
+    if (auto *MulImm = dyn_cast<ConstantSDNode>(Op.getOperand(0))) {
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Could this just use construct known bits of both sides and use KnownBits::mul? It might be able to get value out of the low bits then too.


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Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1147
+    bool Negative = false;
+    if ((Negative = VScaleResultUpperbound < 0))
+      VScaleResultUpperbound = -VScaleResultUpperbound;
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The `Negative =` needn't be part of the if.


Repository:
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  https://reviews.llvm.org/D138424/new/

https://reviews.llvm.org/D138424