[PATCH] D138424: [TargetLowering][AArch64] Teach DemandedBits about VSCALE and SVE CNTx

[Benjamin Maxwell via Phabricator via llvm-commits]

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This now allows DemandedBits to see vscale will be a rather small value
(at most 16 on AArch64) multiplied by some constant. Likewise for the
AArch64 specific SVE count intrinsics. With this various redundant
operations (ands, zexts, sexts, etc) can be eliminated.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D138424

Files:
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/vscale-and-sve-cnt-demandedbits.ll

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