[PATCH] D137931: [RISCV] Don't use zero-stride vector load for gather if not optimized

[Philip Reames via Phabricator via llvm-commits]

reames accepted this revision.
reames added a comment.
This revision is now accepted and ready to land.

LGTM



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Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store-asm.ll:230
+; NOT-OPTIMIZED-NEXT:    vle8.v v8, (a6)
+; NOT-OPTIMIZED-NEXT:    vadd.vx v8, v8, a5
+; NOT-OPTIMIZED-NEXT:    vse8.v v8, (a6)
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Hm, this test case is interesting.

This is a case where even with a fast broadcast load, putting the value into a scalar allows the splat to be folded into the using instruction.  This trades a scalar register for a vector one, and might be generally interesting.

Maybe a case to give some further thought, definitely not blocking for this patch.  


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D137931/new/

https://reviews.llvm.org/D137931