[PATCH] D137931: [RISCV] Don't use zero-stride vector load for gather if not optimized

[Wang Pengcheng via Phabricator via llvm-commits]

pcwang-thead added a comment.

In D137931#3925757 <https://reviews.llvm.org/D137931#3925757>, @reames wrote:

> This isn't correct.  The strided load can be masked.   For the case where all lanes are masked off, executing the scalar load is unsound and could introduce a fault.
>
> You could allow any mask where you can prove at least one lane active, or make the scalar store conditional, but there's a bunch of complexity there.  As a starting point, I suggest you restrict your transformation to when the instruction is unmasked.

Thanks. I didn't consider these situations before.

I tried to transform masked loads to `scalar load + splat + vrgather`, but it may not worth doing it as three instructions are needed. And for **runtime** all-zeros-mask, we may take some costs to handle it. So, I think we can only handle unmasked loads for now. :-)


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https://reviews.llvm.org/D137931