[PATCH] D137931: [RISCV] Don't use zero-stride vector load for gather if not optimized

[Wang Pengcheng via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGa214c521f876: [RISCV] Don't use zero-stride vector load for gather if not optimized (authored by pcwang-thead).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D137931/new/

https://reviews.llvm.org/D137931

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store-asm.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D137931.475657.patch
Type: text/x-patch
Size: 6986 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20221116/38ddf05e/attachment.bin>