[PATCH] D137931: [RISCV] Don't use zero-stride vector load for gather if not optimized

[Wang Pengcheng via Phabricator via llvm-commits]

pcwang-thead updated this revision to Diff 475353.
pcwang-thead added a comment.

Restrict this to unmasked loads only.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D137931/new/

https://reviews.llvm.org/D137931

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store-asm.ll

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