[PATCH] D137931: [RISCV] Don't use zero-stride vector load for gather if not optimized

[Philip Reames via Phabricator via llvm-commits]

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This isn't correct.  The strided load can be masked.   For the case where all lanes are masked off, executing the scalar load is unsound and could introduce a fault.

You could allow any mask where you can prove at least one lane active, or make the scalar store conditional, but there's a bunch of complexity there.  As a starting point, I suggest you restrict your transformation to when the instruction is unmasked.


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https://reviews.llvm.org/D137931