[PATCH] D137931: [RISCV] Don't use zero-stride vector load for gather if not optimized

[Wang Pengcheng via Phabricator via llvm-commits]

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We may form a zero-stride vector load when lowering gather to strided
load. As what D137699 <https://reviews.llvm.org/D137699> has done, we use `load+splat` for this form if
there is no optimized implementation.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D137931

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store-asm.ll

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