[PATCH] D137704: [RISCV] Make lowerVECTOR_SHUFFLEAsVNSRL support more vnsrl shuffle pattern.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D137704#3924065 <https://reviews.llvm.org/D137704#3924065>, @HanKuanChen wrote:

> In D137704#3924061 <https://reviews.llvm.org/D137704#3924061>, @craig.topper wrote:
>
>> In D137704#3924035 <https://reviews.llvm.org/D137704#3924035>, @HanKuanChen wrote:
>>
>>> In D137704#3924007 <https://reviews.llvm.org/D137704#3924007>, @craig.topper wrote:
>>>
>>>> This test crashes
>>>>
>>>>   define void @vnsrl_2_undef_float(ptr %in, ptr %out) {
>>>>   entry:
>>>>     %0 = load <32 x float>, ptr %in, align 4
>>>>     %1 = shufflevector <32 x float> %0, <32 x float> poison, <16 x i32> <i32 1, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
>>>>     store <16 x float> %1, ptr %out, align 4
>>>>     ret void
>>>>   }
>>>
>>> I will merge and close https://reviews.llvm.org/D137904 to solve this test.
>>
>> How does D137904 <https://reviews.llvm.org/D137904> solve this? That patch is marked NFC
>
>
>
>   t7: v32f32,ch = load<(load (s1024) from %ir.in, align 4)> t0, t2, undef:i64
>   t9: v16f32 = extract_subvector t7, Constant:i64<0>
>   t11: v16f32 = vector_shuffle<1,3,u,u,u,u,u,u,u,u,u,u,u,u,u,u> t9, undef:v16f32
>
> I expect we use `getSingleShuffleSource` to get `t7` instead of `t9`. Then we check whether the type of source and destination can match vnsrl rule.
> This test has a 2 `Difference`, and source is `v32f32` and destination is `v16f32`, which is valid.

I don't think that will fix it. The same test crashes if you change the shuffle mask to `<i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>`. That cases should have two extract_subvectors.


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https://reviews.llvm.org/D137704