[PATCH] D137699: [RISCV] Don't use zero-stride vector load if there's no optimized u-arch
Wang Pengcheng via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Sun Nov 13 21:50:07 PST 2022
pcwang-thead added a comment.
In D137699#3921845 <https://reviews.llvm.org/D137699#3921845>, @reames wrote:
> LGTM
>
> If you're interested in optimizing for such a target, I'd suggest a follow up. We should probably be canonicalizing in the other direction (i.e. replace a zero stride load with a load and splat). A zero stride load can probably be matched during gather lowering.
Thanks! I will have a try.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D137699/new/
https://reviews.llvm.org/D137699
More information about the llvm-commits
mailing list