[llvm] 8b3f783 - [X86] Reduce unnecessary instregex for AlderlakeP schedule model
Haohai Wen via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 11 20:32:20 PST 2022
Author: Haohai Wen
Date: 2022-11-12T12:32:08+08:00
New Revision: 8b3f7833e0d2d6be0392831ffeb2edccc5197522
URL: https://github.com/llvm/llvm-project/commit/8b3f7833e0d2d6be0392831ffeb2edccc5197522
DIFF: https://github.com/llvm/llvm-project/commit/8b3f7833e0d2d6be0392831ffeb2edccc5197522.diff
LOG: [X86] Reduce unnecessary instregex for AlderlakeP schedule model
Using instregex for simple instruction opcode is much slower than
instrs. This patch replaces them with instrs.
Github issue: 35303
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D137841
Added:
Modified:
llvm/lib/Target/X86/X86SchedAlderlakeP.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86SchedAlderlakeP.td b/llvm/lib/Target/X86/X86SchedAlderlakeP.td
index 4278c436d1f96..f882a13e9686c 100644
--- a/llvm/lib/Target/X86/X86SchedAlderlakeP.td
+++ b/llvm/lib/Target/X86/X86SchedAlderlakeP.td
@@ -515,93 +515,100 @@ def : WriteRes<WriteZero, []>;
// Infered SchedWriteRes and InstRW definition.
-def ADLPWriteResGroup0 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup0 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort02_03, ADLPPort02_03_07, ADLPPort04]> {
+ let Latency = 7;
+ let NumMicroOps = 3;
+}
+def : InstRW<[ADLPWriteResGroup0], (instregex "^A(OR|ADD|XOR)64mr$")>;
+def : InstRW<[ADLPWriteResGroup0], (instrs AAND64mr)>;
+
+def ADLPWriteResGroup1 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
let ResourceCycles = [2, 1, 1, 1, 1];
let Latency = 12;
let NumMicroOps = 6;
}
-def : InstRW<[ADLPWriteResGroup0, ReadAfterLd, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^(ADC|SBB)(16|32|64)mr$")>;
+def : InstRW<[ADLPWriteResGroup1, ReadAfterLd, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^(ADC|SBB)(16|32|64)mr$")>;
-def ADLPWriteResGroup1 : SchedWriteRes<[ADLPPort00_06, ADLPPort02_03_11]> {
+def ADLPWriteResGroup2 : SchedWriteRes<[ADLPPort00_06, ADLPPort02_03_11]> {
let Latency = 6;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup1], (instregex "^JMP(16|32|64)m$",
+def : InstRW<[ADLPWriteResGroup2], (instregex "^JMP(16|32|64)m$",
"^RET(16|32)$",
"^RORX(32|64)mi$")>;
-def : InstRW<[ADLPWriteResGroup1, ReadAfterLd, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^(ADC|SBB)(8|16|32|64)rm$",
+def : InstRW<[ADLPWriteResGroup2, ReadAfterLd, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^(ADC|SBB)(8|16|32|64)rm$",
"^AD(C|O)X(32|64)rm$")>;
-def ADLPWriteResGroup2 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup3 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
let Latency = 13;
let NumMicroOps = 5;
}
-def : InstRW<[ADLPWriteResGroup2], (instregex "^(ADC|SBB)8mi$")>;
+def : InstRW<[ADLPWriteResGroup3], (instregex "^(ADC|SBB)8mi$")>;
-def ADLPWriteResGroup3 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup4 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
let ResourceCycles = [2, 1, 1, 1, 1];
let Latency = 13;
let NumMicroOps = 6;
}
-def : InstRW<[ADLPWriteResGroup3, ReadAfterLd, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^(ADC|SBB)8mr$")>;
+def : InstRW<[ADLPWriteResGroup4, ReadAfterLd, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^(ADC|SBB)8mr$")>;
-def ADLPWriteResGroup4 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
+def ADLPWriteResGroup5 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
let Latency = 6;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup4], (instregex "^CMP(8|16|32)mi$",
+def : InstRW<[ADLPWriteResGroup5], (instregex "^CMP(8|16|32)mi$",
"^CMP(16|32|64)mi8$",
- "^CMP64mi32$",
"^MOV(8|16)rm$",
- "^MOVZX16rm8$",
"^POP(16|32)r$")>;
-def : InstRW<[ADLPWriteResGroup4, ReadAfterLd], (instregex "^(ADD|CMP|SUB)(8|16|32|64)rm$",
+def : InstRW<[ADLPWriteResGroup5], (instrs CMP64mi32,
+ MOVZX16rm8)>;
+def : InstRW<[ADLPWriteResGroup5, ReadAfterLd], (instregex "^(ADD|CMP|SUB)(8|16|32|64)rm$",
"^(OR|AND|XOR)(8|16|32)rm$")>;
-def : InstRW<[ADLPWriteResGroup4, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^CMP(8|16|32|64)mr$")>;
+def : InstRW<[ADLPWriteResGroup5, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^CMP(8|16|32|64)mr$")>;
-def ADLPWriteResGroup5 : SchedWriteRes<[]> {
+def ADLPWriteResGroup6 : SchedWriteRes<[]> {
let NumMicroOps = 0;
}
-def : InstRW<[ADLPWriteResGroup5], (instregex "^(ADD|SUB)64ri8$",
- "^CLC$",
- "^(DE|IN)C64r$",
- "^MOV64rr$",
- "^MOV64rr_REV$")>;
+def : InstRW<[ADLPWriteResGroup6], (instregex "^(ADD|SUB)64ri8$",
+ "^(DE|IN)C64r$")>;
+def : InstRW<[ADLPWriteResGroup6], (instrs CLC,
+ MOV64rr,
+ MOV64rr_REV)>;
-def ADLPWriteResGroup6 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup7 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
let Latency = 13;
let NumMicroOps = 4;
}
-def : InstRW<[ADLPWriteResGroup6], (instregex "^(OR|ADD|SUB|XOR)8mi$",
- "^AND8mi$",
- "^(DEC|NEG|NOT)8m$",
- "^INC8m$")>;
-def : InstRW<[ADLPWriteResGroup6, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^(OR|ADD|SUB|XOR)8mr$",
- "^AND8mr$")>;
+def : InstRW<[ADLPWriteResGroup7], (instregex "^(OR|ADD|SUB|XOR)8mi$",
+ "^(DEC|NEG|NOT)8m$")>;
+def : InstRW<[ADLPWriteResGroup7], (instrs AND8mi,
+ INC8m)>;
+def : InstRW<[ADLPWriteResGroup7, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^(OR|ADD|SUB|XOR)8mr$")>;
+def : InstRW<[ADLPWriteResGroup7, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instrs AND8mr)>;
-def ADLPWriteResGroup7 : SchedWriteRes<[ADLPPort01_05, ADLPPort02_03_11]> {
+def ADLPWriteResGroup8 : SchedWriteRes<[ADLPPort01_05, ADLPPort02_03_11]> {
let Latency = 10;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup7, ReadAfterVecLd], (instregex "^(V?)(ADD|SUB)SSrm_Int$")>;
+def : InstRW<[ADLPWriteResGroup8, ReadAfterVecLd], (instregex "^(V?)(ADD|SUB)SSrm_Int$")>;
-def ADLPWriteResGroup8 : SchedWriteRes<[ADLPPort01_05]> {
+def ADLPWriteResGroup9 : SchedWriteRes<[ADLPPort01_05]> {
let Latency = 3;
}
-def : InstRW<[ADLPWriteResGroup8], (instregex "^(V?)(ADD|SUB)SSrr_Int$")>;
+def : InstRW<[ADLPWriteResGroup9], (instregex "^(V?)(ADD|SUB)SSrr_Int$")>;
-def ADLPWriteResGroup9 : SchedWriteRes<[ADLPPort02_03, ADLPPort05]> {
+def ADLPWriteResGroup10 : SchedWriteRes<[ADLPPort02_03, ADLPPort05]> {
let ResourceCycles = [1, 2];
let Latency = 13;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup9], (instregex "^(ADD|SUB)_FI(16|32)m$",
- "^SUBR_FI(16|32)m$")>;
+def : InstRW<[ADLPWriteResGroup10], (instregex "^(ADD|SUB)_FI(16|32)m$",
+ "^SUBR_FI(16|32)m$")>;
-def ADLPWriteResGroup10 : SchedWriteRes<[ADLPPort00_01_05_06_10]> {
+def ADLPWriteResGroup11 : SchedWriteRes<[ADLPPort00_01_05_06_10]> {
let Latency = 2;
}
-def : InstRW<[ADLPWriteResGroup10], (instregex "^(OR|AND|XOR)(16|32|64)ri8$",
+def : InstRW<[ADLPWriteResGroup11], (instregex "^(OR|AND|XOR)(16|32|64)ri8$",
"^(OR|AND|XOR)(8|16|32|64)rr$",
"^(OR|AND|XOR)(32|64)i32$",
"^(OR|AND|XOR)(8|32)ri$",
@@ -609,1840 +616,1840 @@ def : InstRW<[ADLPWriteResGroup10], (instregex "^(OR|AND|XOR)(16|32|64)ri8$",
"^(OR|AND|XOR)8i8$",
"^TEST(8|16|32|64)rr$",
"^TEST(32|64)i32$",
- "^TEST(8|32)ri$",
- "^TEST64ri32$",
- "^TEST8i8$")>;
+ "^TEST(8|32)ri$")>;
+def : InstRW<[ADLPWriteResGroup11], (instrs TEST64ri32,
+ TEST8i8)>;
-def ADLPWriteResGroup11 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
+def ADLPWriteResGroup12 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
let Latency = 7;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup11], (instregex "^TEST(8|16|32)mi$",
- "^TEST64mi32$")>;
-def : InstRW<[ADLPWriteResGroup11, ReadAfterLd], (instregex "^(OR|AND|XOR)64rm$")>;
-def : InstRW<[ADLPWriteResGroup11, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^TEST(8|16|32|64)mr$")>;
+def : InstRW<[ADLPWriteResGroup12], (instregex "^TEST(8|16|32)mi$")>;
+def : InstRW<[ADLPWriteResGroup12], (instrs TEST64mi32)>;
+def : InstRW<[ADLPWriteResGroup12, ReadAfterLd], (instregex "^(OR|AND|XOR)64rm$")>;
+def : InstRW<[ADLPWriteResGroup12, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^TEST(8|16|32|64)mr$")>;
-def ADLPWriteResGroup12 : SchedWriteRes<[ADLPPort01_05_10, ADLPPort02_03_11]> {
+def ADLPWriteResGroup13 : SchedWriteRes<[ADLPPort01_05_10, ADLPPort02_03_11]> {
let Latency = 7;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup12, ReadAfterLd], (instregex "^ANDN(32|64)rm$")>;
+def : InstRW<[ADLPWriteResGroup13, ReadAfterLd], (instregex "^ANDN(32|64)rm$")>;
-def ADLPWriteResGroup13 : SchedWriteRes<[ADLPPort01_05_10]> {
+def ADLPWriteResGroup14 : SchedWriteRes<[ADLPPort01_05_10]> {
let Latency = 2;
}
-def : InstRW<[ADLPWriteResGroup13], (instregex "^ANDN(32|64)rr$")>;
+def : InstRW<[ADLPWriteResGroup14], (instregex "^ANDN(32|64)rr$")>;
-def ADLPWriteResGroup14 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11]> {
+def ADLPWriteResGroup15 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11]> {
let ResourceCycles = [5, 2, 1, 1];
let Latency = 10;
let NumMicroOps = 9;
}
-def : InstRW<[ADLPWriteResGroup14], (instregex "^BT64mr$")>;
+def : InstRW<[ADLPWriteResGroup15], (instrs BT64mr)>;
-def ADLPWriteResGroup15 : SchedWriteRes<[ADLPPort01]> {
+def ADLPWriteResGroup16 : SchedWriteRes<[ADLPPort01]> {
let Latency = 3;
}
-def : InstRW<[ADLPWriteResGroup15], (instregex "^(B|PEX)T64rr$",
+def : InstRW<[ADLPWriteResGroup16], (instregex "^(B|PEX)T64rr$",
"^BT(C|R|S)64rr$",
- "^PDEP(32|64)rr$",
- "^PEXT32rr$")>;
+ "^PDEP(32|64)rr$")>;
+def : InstRW<[ADLPWriteResGroup16], (instrs PEXT32rr)>;
-def ADLPWriteResGroup16 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup17 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
let ResourceCycles = [4, 2, 1, 1, 1, 1];
let Latency = 17;
let NumMicroOps = 10;
}
-def : InstRW<[ADLPWriteResGroup16], (instregex "^BT(C|R|S)64mr$")>;
+def : InstRW<[ADLPWriteResGroup17], (instregex "^BT(C|R|S)64mr$")>;
-def ADLPWriteResGroup17 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup18 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
let Latency = 7;
let NumMicroOps = 5;
}
-def : InstRW<[ADLPWriteResGroup17], (instregex "^CALL(16|32|64)m$")>;
+def : InstRW<[ADLPWriteResGroup18], (instregex "^CALL(16|32|64)m$")>;
-def ADLPWriteResGroup18 : SchedWriteRes<[ADLPPort00_06, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup19 : SchedWriteRes<[ADLPPort00_06, ADLPPort04_09, ADLPPort07_08]> {
let Latency = 3;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup18], (instregex "^CALL(16|32|64)r$")>;
+def : InstRW<[ADLPWriteResGroup19], (instregex "^CALL(16|32|64)r$")>;
-def ADLPWriteResGroup19 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup20 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
let Latency = 3;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup19], (instregex "^CALL64pcrel32$",
- "^MFENCE$")>;
+def : InstRW<[ADLPWriteResGroup20], (instrs CALL64pcrel32,
+ MFENCE)>;
-def ADLPWriteResGroup20 : SchedWriteRes<[ADLPPort01_05]>;
-def : InstRW<[ADLPWriteResGroup20], (instregex "^C(BW|DQE|WDE)$",
+def ADLPWriteResGroup21 : SchedWriteRes<[ADLPPort01_05]>;
+def : InstRW<[ADLPWriteResGroup21], (instregex "^C(BW|DQE|WDE)$",
"^(V?)MOVS(H|L)DUPrr$",
"^(V?)SHUFP(D|S)rri$",
"^VMOVS(H|L)DUPYrr$",
- "^VPBLENDWYrri$",
"^VSHUFP(D|S)Yrri$")>;
+def : InstRW<[ADLPWriteResGroup21], (instrs VPBLENDWYrri)>;
-def ADLPWriteResGroup21 : SchedWriteRes<[ADLPPort00_06]>;
-def : InstRW<[ADLPWriteResGroup21], (instregex "^C(DQ|QO|LAC)$",
- "^STAC$")>;
+def ADLPWriteResGroup22 : SchedWriteRes<[ADLPPort00_06]>;
+def : InstRW<[ADLPWriteResGroup22], (instregex "^C(DQ|QO|LAC)$")>;
+def : InstRW<[ADLPWriteResGroup22], (instrs STAC)>;
-def ADLPWriteResGroup22 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06]> {
+def ADLPWriteResGroup23 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06]> {
let Latency = 3;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup22], (instregex "^CLD$")>;
+def : InstRW<[ADLPWriteResGroup23], (instrs CLD)>;
-def ADLPWriteResGroup23 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup24 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort04_09, ADLPPort07_08]> {
let Latency = 3;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup23], (instregex "^CLDEMOTE$")>;
+def : InstRW<[ADLPWriteResGroup24], (instrs CLDEMOTE)>;
-def ADLPWriteResGroup24 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup25 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort04_09, ADLPPort07_08]> {
let Latency = 2;
let NumMicroOps = 4;
}
-def : InstRW<[ADLPWriteResGroup24], (instregex "^CLFLUSH$")>;
+def : InstRW<[ADLPWriteResGroup25], (instrs CLFLUSH)>;
-def ADLPWriteResGroup25 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup26 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort04_09, ADLPPort07_08]> {
let Latency = 2;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup25], (instregex "^CLFLUSHOPT$")>;
+def : InstRW<[ADLPWriteResGroup26], (instrs CLFLUSHOPT)>;
-def ADLPWriteResGroup26 : SchedWriteRes<[ADLPPort00_06, ADLPPort01]> {
+def ADLPWriteResGroup27 : SchedWriteRes<[ADLPPort00_06, ADLPPort01]> {
let ResourceCycles = [2, 1];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup26], (instregex "^CLI$")>;
+def : InstRW<[ADLPWriteResGroup27], (instrs CLI)>;
-def ADLPWriteResGroup27 : SchedWriteRes<[ADLPPort00_06, ADLPPort01, ADLPPort05]> {
+def ADLPWriteResGroup28 : SchedWriteRes<[ADLPPort00_06, ADLPPort01, ADLPPort05]> {
let ResourceCycles = [6, 1, 3];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 10;
}
-def : InstRW<[ADLPWriteResGroup27], (instregex "^CLTS$")>;
+def : InstRW<[ADLPWriteResGroup28], (instrs CLTS)>;
-def ADLPWriteResGroup28 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup29 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort04_09, ADLPPort07_08]> {
let Latency = 5;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup28], (instregex "^CLWB$",
- "^MOV16o(16|32|64)a$")>;
+def : InstRW<[ADLPWriteResGroup29], (instregex "^MOV16o(16|32|64)a$")>;
+def : InstRW<[ADLPWriteResGroup29], (instrs CLWB)>;
-def ADLPWriteResGroup29 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
+def ADLPWriteResGroup30 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
let ResourceCycles = [5, 2];
let Latency = 6;
let NumMicroOps = 7;
}
-def : InstRW<[ADLPWriteResGroup29], (instregex "^CMPS(B|L|Q|W)$")>;
+def : InstRW<[ADLPWriteResGroup30], (instregex "^CMPS(B|L|Q|W)$")>;
-def ADLPWriteResGroup30 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01_05, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup31 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01_05, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [2, 7, 6, 2, 1, 1, 2, 1];
let Latency = 32;
let NumMicroOps = 22;
}
-def : InstRW<[ADLPWriteResGroup30], (instregex "^CMPXCHG16B$")>;
+def : InstRW<[ADLPWriteResGroup31], (instrs CMPXCHG16B)>;
-def ADLPWriteResGroup31 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup32 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
let ResourceCycles = [4, 7, 2, 1, 1, 1];
let Latency = 25;
let NumMicroOps = 16;
}
-def : InstRW<[ADLPWriteResGroup31], (instregex "^CMPXCHG8B$")>;
+def : InstRW<[ADLPWriteResGroup32], (instrs CMPXCHG8B)>;
-def ADLPWriteResGroup32 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup33 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
let ResourceCycles = [1, 2, 1, 1, 1];
let Latency = 13;
let NumMicroOps = 6;
}
-def : InstRW<[ADLPWriteResGroup32], (instregex "^CMPXCHG8rm$")>;
+def : InstRW<[ADLPWriteResGroup33], (instrs CMPXCHG8rm)>;
-def ADLPWriteResGroup33 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_06, ADLPPort01, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup34 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_06, ADLPPort01, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [2, 1, 10, 6, 1, 5, 1];
let Latency = 18;
let NumMicroOps = 26;
}
-def : InstRW<[ADLPWriteResGroup33], (instregex "^CPUID$")>;
+def : InstRW<[ADLPWriteResGroup34], (instrs CPUID)>;
-def ADLPWriteResGroup34 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort02_03_11]> {
+def ADLPWriteResGroup35 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort02_03_11]> {
let Latency = 26;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup34], (instregex "^(V?)CVT(T?)SD2SIrm_Int$")>;
+def : InstRW<[ADLPWriteResGroup35], (instregex "^(V?)CVT(T?)SD2SIrm_Int$")>;
-def ADLPWriteResGroup35 : SchedWriteRes<[ADLPPort00_01, ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup36 : SchedWriteRes<[ADLPPort00_01, ADLPPort02_03_11, ADLPPort05]> {
let Latency = 12;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup35, ReadAfterVecLd], (instregex "^(V?)CVTSI642SSrm_Int$")>;
+def : InstRW<[ADLPWriteResGroup36, ReadAfterVecLd], (instregex "^(V?)CVTSI642SSrm_Int$")>;
-def ADLPWriteResGroup36 : SchedWriteRes<[ADLPPort00_01, ADLPPort05]> {
+def ADLPWriteResGroup37 : SchedWriteRes<[ADLPPort00_01, ADLPPort05]> {
let ResourceCycles = [1, 2];
let Latency = 8;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup36, ReadDefault, ReadInt2Fpu], (instregex "^(V?)CVTSI642SSrr_Int$")>;
+def : InstRW<[ADLPWriteResGroup37, ReadDefault, ReadInt2Fpu], (instregex "^(V?)CVTSI642SSrr_Int$")>;
-def ADLPWriteResGroup37 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort05]> {
+def ADLPWriteResGroup38 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort05]> {
let Latency = 8;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup37], (instregex "^(V?)CVT(T?)SS2SI64rr_Int$")>;
+def : InstRW<[ADLPWriteResGroup38], (instregex "^(V?)CVT(T?)SS2SI64rr_Int$")>;
-def ADLPWriteResGroup38 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06]> {
+def ADLPWriteResGroup39 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06]> {
let Latency = 2;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup38], (instregex "^CWD$",
- "^J(E|R)CXZ$")>;
+def : InstRW<[ADLPWriteResGroup39], (instregex "^J(E|R)CXZ$")>;
+def : InstRW<[ADLPWriteResGroup39], (instrs CWD)>;
-def ADLPWriteResGroup39 : SchedWriteRes<[ADLPPort00_01_05_06]>;
-def : InstRW<[ADLPWriteResGroup39], (instregex "^DEC16r_alt$",
- "^(LD|ST)_Frr$",
+def ADLPWriteResGroup40 : SchedWriteRes<[ADLPPort00_01_05_06]>;
+def : InstRW<[ADLPWriteResGroup40], (instregex "^(LD|ST)_Frr$",
"^MOV16s(m|r)$",
- "^MOV(32|64)sr$",
- "^SALC$",
- "^ST_FPrr$",
- "^SYSCALL$")>;
+ "^MOV(32|64)sr$")>;
+def : InstRW<[ADLPWriteResGroup40], (instrs DEC16r_alt,
+ SALC,
+ ST_FPrr,
+ SYSCALL)>;
-def ADLPWriteResGroup40 : SchedWriteRes<[ADLPPort00_06, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup41 : SchedWriteRes<[ADLPPort00_06, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
let Latency = 7;
}
-def : InstRW<[ADLPWriteResGroup40], (instregex "^DEC32r_alt$")>;
+def : InstRW<[ADLPWriteResGroup41], (instrs DEC32r_alt)>;
-def ADLPWriteResGroup41 : SchedWriteRes<[ADLPPort00, ADLPPort02_03, ADLPPort05]> {
+def ADLPWriteResGroup42 : SchedWriteRes<[ADLPPort00, ADLPPort02_03, ADLPPort05]> {
let Latency = 30;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup41], (instregex "^DIVR_FI(16|32)m$")>;
+def : InstRW<[ADLPWriteResGroup42], (instregex "^DIVR_FI(16|32)m$")>;
-def ADLPWriteResGroup42 : SchedWriteRes<[ADLPPort00, ADLPPort02_03_11]> {
+def ADLPWriteResGroup43 : SchedWriteRes<[ADLPPort00, ADLPPort02_03_11]> {
let Latency = 18;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup42, ReadAfterVecLd], (instregex "^(V?)DIVSSrm_Int$")>;
+def : InstRW<[ADLPWriteResGroup43, ReadAfterVecLd], (instregex "^(V?)DIVSSrm_Int$")>;
-def ADLPWriteResGroup43 : SchedWriteRes<[ADLPPort00]> {
+def ADLPWriteResGroup44 : SchedWriteRes<[ADLPPort00]> {
let Latency = 11;
}
-def : InstRW<[ADLPWriteResGroup43], (instregex "^(V?)DIVSSrr_Int$")>;
+def : InstRW<[ADLPWriteResGroup44], (instregex "^(V?)DIVSSrr_Int$")>;
-def ADLPWriteResGroup44 : SchedWriteRes<[ADLPPort00, ADLPPort02_03]> {
+def ADLPWriteResGroup45 : SchedWriteRes<[ADLPPort00, ADLPPort02_03]> {
let Latency = 22;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup44], (instregex "^DIV_F(32|64)m$")>;
+def : InstRW<[ADLPWriteResGroup45], (instregex "^DIV_F(32|64)m$")>;
-def ADLPWriteResGroup45 : SchedWriteRes<[ADLPPort00, ADLPPort02_03, ADLPPort05]> {
+def ADLPWriteResGroup46 : SchedWriteRes<[ADLPPort00, ADLPPort02_03, ADLPPort05]> {
let Latency = 25;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup45], (instregex "^DIV_FI(16|32)m$")>;
+def : InstRW<[ADLPWriteResGroup46], (instregex "^DIV_FI(16|32)m$")>;
-def ADLPWriteResGroup46 : SchedWriteRes<[ADLPPort00]> {
+def ADLPWriteResGroup47 : SchedWriteRes<[ADLPPort00]> {
let Latency = 20;
}
-def : InstRW<[ADLPWriteResGroup46], (instregex "^DIV_F(P?)rST0$",
- "^DIV_FST0r$")>;
+def : InstRW<[ADLPWriteResGroup47], (instregex "^DIV_F(P?)rST0$")>;
+def : InstRW<[ADLPWriteResGroup47], (instrs DIV_FST0r)>;
-def ADLPWriteResGroup47 : SchedWriteRes<[ADLPPort00, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup48 : SchedWriteRes<[ADLPPort00, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [2, 21, 2, 14, 4, 9, 5];
let Latency = 126;
let NumMicroOps = 57;
}
-def : InstRW<[ADLPWriteResGroup47], (instregex "^ENTER$")>;
+def : InstRW<[ADLPWriteResGroup48], (instrs ENTER)>;
-def ADLPWriteResGroup48 : SchedWriteRes<[ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup49 : SchedWriteRes<[ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let Latency = 12;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup48], (instregex "^(V?)EXTRACTPSmr$",
- "^SMSW16m$")>;
+def : InstRW<[ADLPWriteResGroup49], (instregex "^(V?)EXTRACTPSmr$")>;
+def : InstRW<[ADLPWriteResGroup49], (instrs SMSW16m)>;
-def ADLPWriteResGroup49 : SchedWriteRes<[ADLPPort00, ADLPPort05]> {
+def ADLPWriteResGroup50 : SchedWriteRes<[ADLPPort00, ADLPPort05]> {
let Latency = 4;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup49], (instregex "^(V?)EXTRACTPSrr$",
- "^MMX_PEXTRWrr$")>;
+def : InstRW<[ADLPWriteResGroup50], (instregex "^(V?)EXTRACTPSrr$")>;
+def : InstRW<[ADLPWriteResGroup50], (instrs MMX_PEXTRWrr)>;
-def ADLPWriteResGroup50 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort02_03, ADLPPort02_03_07, ADLPPort04, ADLPPort06]> {
+def ADLPWriteResGroup51 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort02_03, ADLPPort02_03_07, ADLPPort04, ADLPPort06]> {
let Latency = 7;
let NumMicroOps = 5;
}
-def : InstRW<[ADLPWriteResGroup50], (instregex "^FARCALL64m$")>;
+def : InstRW<[ADLPWriteResGroup51], (instrs FARCALL64m)>;
-def ADLPWriteResGroup51 : SchedWriteRes<[ADLPPort02_03, ADLPPort06]> {
+def ADLPWriteResGroup52 : SchedWriteRes<[ADLPPort02_03, ADLPPort06]> {
let Latency = 6;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup51], (instregex "^FARJMP64m$")>;
+def : InstRW<[ADLPWriteResGroup52], (instrs FARJMP64m)>;
-def ADLPWriteResGroup52 : SchedWriteRes<[ADLPPort02_03_07, ADLPPort04]> {
+def ADLPWriteResGroup53 : SchedWriteRes<[ADLPPort02_03_07, ADLPPort04]> {
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup52], (instregex "^FBSTPm$",
- "^(V?)MASKMOVDQU((64)?)$",
- "^ST_FP(32|64|80)m$",
- "^VMPTRSTm$")>;
+def : InstRW<[ADLPWriteResGroup53], (instregex "^(V?)MASKMOVDQU((64)?)$",
+ "^ST_FP(32|64|80)m$")>;
+def : InstRW<[ADLPWriteResGroup53], (instrs FBSTPm,
+ VMPTRSTm)>;
-def ADLPWriteResGroup53 : SchedWriteRes<[ADLPPort00_05]> {
+def ADLPWriteResGroup54 : SchedWriteRes<[ADLPPort00_05]> {
let ResourceCycles = [2];
let Latency = 2;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup53], (instregex "^FDECSTP$")>;
+def : InstRW<[ADLPWriteResGroup54], (instrs FDECSTP)>;
-def ADLPWriteResGroup54 : SchedWriteRes<[ADLPPort02_03, ADLPPort05]> {
+def ADLPWriteResGroup55 : SchedWriteRes<[ADLPPort02_03, ADLPPort05]> {
let ResourceCycles = [1, 2];
let Latency = 11;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup54], (instregex "^FICOM(P?)(16|32)m$")>;
+def : InstRW<[ADLPWriteResGroup55], (instregex "^FICOM(P?)(16|32)m$")>;
-def ADLPWriteResGroup55 : SchedWriteRes<[ADLPPort00_05]>;
-def : InstRW<[ADLPWriteResGroup55], (instregex "^FINCSTP$",
- "^FNOP$",
- "^MMX_P(ADD|SUB)(B|D|Q|W)rr$")>;
+def ADLPWriteResGroup56 : SchedWriteRes<[ADLPPort00_05]>;
+def : InstRW<[ADLPWriteResGroup56], (instregex "^MMX_P(ADD|SUB)(B|D|Q|W)rr$")>;
+def : InstRW<[ADLPWriteResGroup56], (instrs FINCSTP,
+ FNOP)>;
-def ADLPWriteResGroup56 : SchedWriteRes<[ADLPPort00, ADLPPort00_05, ADLPPort02_03]> {
+def ADLPWriteResGroup57 : SchedWriteRes<[ADLPPort00, ADLPPort00_05, ADLPPort02_03]> {
let Latency = 7;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup56], (instregex "^FLDCW16m$")>;
+def : InstRW<[ADLPWriteResGroup57], (instrs FLDCW16m)>;
-def ADLPWriteResGroup57 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06, ADLPPort00_05, ADLPPort00_06, ADLPPort02_03]> {
+def ADLPWriteResGroup58 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06, ADLPPort00_05, ADLPPort00_06, ADLPPort02_03]> {
let ResourceCycles = [2, 39, 5, 10, 8];
let Latency = 62;
let NumMicroOps = 64;
}
-def : InstRW<[ADLPWriteResGroup57], (instregex "^FLDENVm$")>;
+def : InstRW<[ADLPWriteResGroup58], (instrs FLDENVm)>;
-def ADLPWriteResGroup58 : SchedWriteRes<[ADLPPort00_01_05_06]> {
+def ADLPWriteResGroup59 : SchedWriteRes<[ADLPPort00_01_05_06]> {
let ResourceCycles = [4];
let Latency = 4;
let NumMicroOps = 4;
}
-def : InstRW<[ADLPWriteResGroup58], (instregex "^FNCLEX$")>;
+def : InstRW<[ADLPWriteResGroup59], (instrs FNCLEX)>;
-def ADLPWriteResGroup59 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort00_05, ADLPPort05]> {
+def ADLPWriteResGroup60 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort00_05, ADLPPort05]> {
let ResourceCycles = [6, 3, 6];
let Latency = 75;
let NumMicroOps = 15;
}
-def : InstRW<[ADLPWriteResGroup59], (instregex "^FNINIT$")>;
+def : InstRW<[ADLPWriteResGroup60], (instrs FNINIT)>;
-def ADLPWriteResGroup60 : SchedWriteRes<[ADLPPort02_03_07, ADLPPort04, ADLPPort06]> {
+def ADLPWriteResGroup61 : SchedWriteRes<[ADLPPort02_03_07, ADLPPort04, ADLPPort06]> {
let Latency = 2;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup60], (instregex "^FNSTCW16m$")>;
+def : InstRW<[ADLPWriteResGroup61], (instrs FNSTCW16m)>;
-def ADLPWriteResGroup61 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06]> {
+def ADLPWriteResGroup62 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06]> {
let Latency = 3;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup61], (instregex "^FNSTSW16r$")>;
+def : InstRW<[ADLPWriteResGroup62], (instrs FNSTSW16r)>;
-def ADLPWriteResGroup62 : SchedWriteRes<[ADLPPort00, ADLPPort02_03_07, ADLPPort04]> {
+def ADLPWriteResGroup63 : SchedWriteRes<[ADLPPort00, ADLPPort02_03_07, ADLPPort04]> {
let Latency = 3;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup62], (instregex "^FNSTSWm$")>;
+def : InstRW<[ADLPWriteResGroup63], (instrs FNSTSWm)>;
-def ADLPWriteResGroup63 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06, ADLPPort00_06, ADLPPort01, ADLPPort02_03_07, ADLPPort04, ADLPPort05, ADLPPort06]> {
+def ADLPWriteResGroup64 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06, ADLPPort00_06, ADLPPort01, ADLPPort02_03_07, ADLPPort04, ADLPPort05, ADLPPort06]> {
let ResourceCycles = [9, 30, 21, 1, 11, 11, 16, 1];
let Latency = 106;
let NumMicroOps = 100;
}
-def : InstRW<[ADLPWriteResGroup63], (instregex "^FSTENVm$")>;
+def : InstRW<[ADLPWriteResGroup64], (instrs FSTENVm)>;
-def ADLPWriteResGroup64 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06, ADLPPort00_05, ADLPPort00_06, ADLPPort01_05, ADLPPort02_03, ADLPPort06]> {
+def ADLPWriteResGroup65 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06, ADLPPort00_05, ADLPPort00_06, ADLPPort01_05, ADLPPort02_03, ADLPPort06]> {
let ResourceCycles = [4, 47, 1, 2, 1, 33, 2];
let Latency = 63;
let NumMicroOps = 90;
}
-def : InstRW<[ADLPWriteResGroup64], (instregex "^FXRSTOR$")>;
+def : InstRW<[ADLPWriteResGroup65], (instrs FXRSTOR)>;
-def ADLPWriteResGroup65 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06, ADLPPort00_05, ADLPPort00_06, ADLPPort01_05, ADLPPort02_03, ADLPPort06]> {
+def ADLPWriteResGroup66 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06, ADLPPort00_05, ADLPPort00_06, ADLPPort01_05, ADLPPort02_03, ADLPPort06]> {
let ResourceCycles = [4, 45, 1, 2, 1, 31, 4];
let Latency = 63;
let NumMicroOps = 88;
}
-def : InstRW<[ADLPWriteResGroup65], (instregex "^FXRSTOR64$")>;
+def : InstRW<[ADLPWriteResGroup66], (instrs FXRSTOR64)>;
-def ADLPWriteResGroup66 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup67 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [2, 5, 10, 10, 2, 38, 5, 38];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 110;
}
-def : InstRW<[ADLPWriteResGroup66], (instregex "^FXSAVE((64)?)$")>;
+def : InstRW<[ADLPWriteResGroup67], (instregex "^FXSAVE((64)?)$")>;
-def ADLPWriteResGroup67 : SchedWriteRes<[ADLPPort00_01, ADLPPort02_03_11]> {
+def ADLPWriteResGroup68 : SchedWriteRes<[ADLPPort00_01, ADLPPort02_03_11]> {
let Latency = 12;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup67, ReadAfterVecXLd], (instregex "^(V?)GF2P8AFFINE((INV)?)QBrmi$",
+def : InstRW<[ADLPWriteResGroup68, ReadAfterVecXLd], (instregex "^(V?)GF2P8AFFINE((INV)?)QBrmi$",
"^(V?)GF2P8MULBrm$",
- "^VGF2P8AFFINE((INV)?)QBYrmi$",
- "^VGF2P8MULBYrm$")>;
+ "^VGF2P8AFFINE((INV)?)QBYrmi$")>;
+def : InstRW<[ADLPWriteResGroup68, ReadAfterVecXLd], (instrs VGF2P8MULBYrm)>;
-def ADLPWriteResGroup68 : SchedWriteRes<[ADLPPort00_01]> {
+def ADLPWriteResGroup69 : SchedWriteRes<[ADLPPort00_01]> {
let Latency = 5;
}
-def : InstRW<[ADLPWriteResGroup68], (instregex "^(V?)GF2P8AFFINE((INV)?)QBrri$",
+def : InstRW<[ADLPWriteResGroup69], (instregex "^(V?)GF2P8AFFINE((INV)?)QBrri$",
"^(V?)GF2P8MULBrr$",
- "^VGF2P8AFFINE((INV)?)QBYrri$",
- "^VGF2P8MULBYrr$")>;
+ "^VGF2P8AFFINE((INV)?)QBYrri$")>;
+def : InstRW<[ADLPWriteResGroup69], (instrs VGF2P8MULBYrr)>;
-def ADLPWriteResGroup69 : SchedWriteRes<[ADLPPort02_03, ADLPPort05]> {
+def ADLPWriteResGroup70 : SchedWriteRes<[ADLPPort02_03, ADLPPort05]> {
let Latency = 10;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup69], (instregex "^ILD_F(16|32|64)m$")>;
+def : InstRW<[ADLPWriteResGroup70], (instregex "^ILD_F(16|32|64)m$")>;
-def ADLPWriteResGroup70 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup71 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort02_03_11, ADLPPort05]> {
let ResourceCycles = [7, 5, 26, 19, 2, 7, 21];
let Latency = 35;
let NumMicroOps = 87;
}
-def : InstRW<[ADLPWriteResGroup70], (instregex "^IN16ri$")>;
+def : InstRW<[ADLPWriteResGroup71], (instrs IN16ri)>;
-def ADLPWriteResGroup71 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup72 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort02_03_11, ADLPPort05]> {
let ResourceCycles = [7, 1, 4, 26, 19, 3, 7, 20];
let Latency = 35;
let NumMicroOps = 87;
}
-def : InstRW<[ADLPWriteResGroup71], (instregex "^IN16rr$")>;
+def : InstRW<[ADLPWriteResGroup72], (instrs IN16rr)>;
-def ADLPWriteResGroup72 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup73 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort02_03_11, ADLPPort05]> {
let ResourceCycles = [7, 6, 28, 21, 2, 10, 20];
let Latency = 35;
let NumMicroOps = 94;
}
-def : InstRW<[ADLPWriteResGroup72], (instregex "^IN32ri$")>;
+def : InstRW<[ADLPWriteResGroup73], (instrs IN32ri)>;
-def ADLPWriteResGroup73 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup74 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort02_03_11, ADLPPort05]> {
let ResourceCycles = [7, 9, 28, 21, 2, 11, 21];
let NumMicroOps = 99;
}
-def : InstRW<[ADLPWriteResGroup73], (instregex "^IN32rr$")>;
+def : InstRW<[ADLPWriteResGroup74], (instrs IN32rr)>;
-def ADLPWriteResGroup74 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup75 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort02_03_11, ADLPPort05]> {
let ResourceCycles = [7, 6, 25, 19, 2, 8, 20];
let Latency = 35;
let NumMicroOps = 87;
}
-def : InstRW<[ADLPWriteResGroup74], (instregex "^IN8ri$")>;
+def : InstRW<[ADLPWriteResGroup75], (instrs IN8ri)>;
-def ADLPWriteResGroup75 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup76 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort02_03_11, ADLPPort05]> {
let ResourceCycles = [7, 6, 25, 19, 2, 7, 20];
let Latency = 35;
let NumMicroOps = 86;
}
-def : InstRW<[ADLPWriteResGroup75], (instregex "^IN8rr$")>;
+def : InstRW<[ADLPWriteResGroup76], (instrs IN8rr)>;
-def ADLPWriteResGroup76 : SchedWriteRes<[ADLPPort00_06]> {
+def ADLPWriteResGroup77 : SchedWriteRes<[ADLPPort00_06]> {
let NumMicroOps = 4;
}
-def : InstRW<[ADLPWriteResGroup76], (instregex "^INC16r_alt$")>;
+def : InstRW<[ADLPWriteResGroup77], (instrs INC16r_alt)>;
-def ADLPWriteResGroup77 : SchedWriteRes<[ADLPPort02_03_11]> {
+def ADLPWriteResGroup78 : SchedWriteRes<[ADLPPort02_03_11]> {
let Latency = 7;
}
-def : InstRW<[ADLPWriteResGroup77], (instregex "^INC32r_alt$",
- "^(V?)MOV(D|SH|SL)DUPrm$",
- "^VBROADCASTSSrm$",
+def : InstRW<[ADLPWriteResGroup78], (instregex "^(V?)MOV(D|SH|SL)DUPrm$",
"^VPBROADCAST(D|Q)rm$")>;
+def : InstRW<[ADLPWriteResGroup78], (instrs INC32r_alt,
+ VBROADCASTSSrm)>;
-def ADLPWriteResGroup78 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup79 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [7, 6, 24, 17, 8, 1, 19, 1];
let Latency = 20;
let NumMicroOps = 83;
}
-def : InstRW<[ADLPWriteResGroup78], (instregex "^INSB$")>;
+def : InstRW<[ADLPWriteResGroup79], (instrs INSB)>;
-def ADLPWriteResGroup79 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup80 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [7, 1, 5, 1, 27, 17, 11, 1, 21, 1];
let Latency = 20;
let NumMicroOps = 92;
}
-def : InstRW<[ADLPWriteResGroup79], (instregex "^INSL$")>;
+def : InstRW<[ADLPWriteResGroup80], (instrs INSL)>;
-def ADLPWriteResGroup80 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup81 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [7, 1, 4, 1, 25, 17, 1, 9, 1, 19, 1];
let Latency = 20;
let NumMicroOps = 86;
}
-def : InstRW<[ADLPWriteResGroup80], (instregex "^INSW$")>;
+def : InstRW<[ADLPWriteResGroup81], (instrs INSW)>;
-def ADLPWriteResGroup81 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup82 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [5, 4, 8, 6, 2, 5, 7, 5];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 42;
}
-def : InstRW<[ADLPWriteResGroup81], (instregex "^INVLPG$")>;
+def : InstRW<[ADLPWriteResGroup82], (instrs INVLPG)>;
-def ADLPWriteResGroup82 : SchedWriteRes<[ADLPPort02_03_07, ADLPPort04, ADLPPort05]> {
+def ADLPWriteResGroup83 : SchedWriteRes<[ADLPPort02_03_07, ADLPPort04, ADLPPort05]> {
let Latency = 4;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup82], (instregex "^IST(T?)_FP(16|32|64)m$",
+def : InstRW<[ADLPWriteResGroup83], (instregex "^IST(T?)_FP(16|32|64)m$",
"^IST_F(16|32)m$")>;
-def ADLPWriteResGroup83 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort00_06]> {
+def ADLPWriteResGroup84 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort00_06]> {
let Latency = 2;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup83], (instregex "^JCXZ$")>;
+def : InstRW<[ADLPWriteResGroup84], (instrs JCXZ)>;
-def ADLPWriteResGroup84 : SchedWriteRes<[]> {
+def ADLPWriteResGroup85 : SchedWriteRes<[]> {
let Latency = 0;
let NumMicroOps = 0;
}
-def : InstRW<[ADLPWriteResGroup84], (instregex "^JMP_1$",
- "^VZEROUPPER$")>;
+def : InstRW<[ADLPWriteResGroup85], (instrs JMP_1,
+ VZEROUPPER)>;
-def ADLPWriteResGroup85 : SchedWriteRes<[ADLPPort00, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup86 : SchedWriteRes<[ADLPPort00, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
let ResourceCycles = [8, 2, 14, 3, 1];
let Latency = 198;
let NumMicroOps = 81;
}
-def : InstRW<[ADLPWriteResGroup85], (instregex "^LAR16rm$")>;
+def : InstRW<[ADLPWriteResGroup86], (instrs LAR16rm)>;
-def ADLPWriteResGroup86 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup87 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort05]> {
let ResourceCycles = [1, 3, 1, 8, 5, 1, 2, 1];
let Latency = 66;
let NumMicroOps = 22;
}
-def : InstRW<[ADLPWriteResGroup86], (instregex "^LAR16rr$")>;
+def : InstRW<[ADLPWriteResGroup87], (instrs LAR16rr)>;
-def ADLPWriteResGroup87 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup88 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
let ResourceCycles = [1, 2, 2, 9, 5, 3, 1];
let Latency = 71;
let NumMicroOps = 85;
}
-def : InstRW<[ADLPWriteResGroup87], (instregex "^LAR32rm$")>;
+def : InstRW<[ADLPWriteResGroup88], (instrs LAR32rm)>;
-def ADLPWriteResGroup88 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup89 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort05]> {
let ResourceCycles = [1, 3, 1, 8, 5, 1, 2, 1];
let Latency = 65;
let NumMicroOps = 22;
}
-def : InstRW<[ADLPWriteResGroup88], (instregex "^LAR(32|64)rr$")>;
+def : InstRW<[ADLPWriteResGroup89], (instregex "^LAR(32|64)rr$")>;
-def ADLPWriteResGroup89 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup90 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
let ResourceCycles = [1, 2, 2, 9, 5, 3, 1];
let Latency = 71;
let NumMicroOps = 87;
}
-def : InstRW<[ADLPWriteResGroup89], (instregex "^LAR64rm$")>;
+def : InstRW<[ADLPWriteResGroup90], (instrs LAR64rm)>;
-def ADLPWriteResGroup90 : SchedWriteRes<[ADLPPort02_03]> {
+def ADLPWriteResGroup91 : SchedWriteRes<[ADLPPort02_03]> {
let Latency = 7;
}
-def : InstRW<[ADLPWriteResGroup90], (instregex "^LD_F(32|64|80)m$")>;
+def : InstRW<[ADLPWriteResGroup91], (instregex "^LD_F(32|64|80)m$")>;
-def ADLPWriteResGroup91 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort01]> {
+def ADLPWriteResGroup92 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort01]> {
let Latency = 2;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup91], (instregex "^LEA16r$")>;
+def : InstRW<[ADLPWriteResGroup92], (instrs LEA16r)>;
-def ADLPWriteResGroup92 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
+def ADLPWriteResGroup93 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
let ResourceCycles = [3, 1];
let Latency = 6;
let NumMicroOps = 4;
}
-def : InstRW<[ADLPWriteResGroup92], (instregex "^LEAVE$",
- "^(LOD|SCA)S(B|W)$",
+def : InstRW<[ADLPWriteResGroup93], (instregex "^(LOD|SCA)S(B|W)$",
"^SCAS(L|Q)$")>;
+def : InstRW<[ADLPWriteResGroup93], (instrs LEAVE)>;
-def ADLPWriteResGroup93 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
+def ADLPWriteResGroup94 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
let ResourceCycles = [2, 1];
let Latency = 6;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup93], (instregex "^LEAVE64$")>;
+def : InstRW<[ADLPWriteResGroup94], (instrs LEAVE64)>;
-def ADLPWriteResGroup94 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup95 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
let ResourceCycles = [1, 2, 4, 3, 2, 1, 1];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 14;
}
-def : InstRW<[ADLPWriteResGroup94], (instregex "^LGDT64m$")>;
+def : InstRW<[ADLPWriteResGroup95], (instrs LGDT64m)>;
-def ADLPWriteResGroup95 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup96 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
let ResourceCycles = [1, 1, 5, 3, 2, 1, 1];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 14;
}
-def : InstRW<[ADLPWriteResGroup95], (instregex "^LIDT64m$")>;
+def : InstRW<[ADLPWriteResGroup96], (instrs LIDT64m)>;
-def ADLPWriteResGroup96 : SchedWriteRes<[ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup97 : SchedWriteRes<[ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
let ResourceCycles = [5, 3, 2, 1, 1];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 12;
}
-def : InstRW<[ADLPWriteResGroup96], (instregex "^LLDT16m$")>;
+def : InstRW<[ADLPWriteResGroup97], (instrs LLDT16m)>;
-def ADLPWriteResGroup97 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup98 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
let ResourceCycles = [1, 4, 3, 1, 1, 1];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 11;
}
-def : InstRW<[ADLPWriteResGroup97], (instregex "^LLDT16r$")>;
+def : InstRW<[ADLPWriteResGroup98], (instrs LLDT16r)>;
-def ADLPWriteResGroup98 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup99 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [1, 1, 2, 8, 3, 1, 2, 7, 2];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 27;
}
-def : InstRW<[ADLPWriteResGroup98], (instregex "^LMSW16m$")>;
+def : InstRW<[ADLPWriteResGroup99], (instrs LMSW16m)>;
-def ADLPWriteResGroup99 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup100 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [5, 7, 1, 2, 5, 2];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 22;
}
-def : InstRW<[ADLPWriteResGroup99], (instregex "^LMSW16r$")>;
+def : InstRW<[ADLPWriteResGroup100], (instrs LMSW16r)>;
-def ADLPWriteResGroup100 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
+def ADLPWriteResGroup101 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
let ResourceCycles = [2, 1];
let Latency = 5;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup100], (instregex "^LODS(L|Q)$")>;
+def : InstRW<[ADLPWriteResGroup101], (instregex "^LODS(L|Q)$")>;
-def ADLPWriteResGroup101 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
+def ADLPWriteResGroup102 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
let ResourceCycles = [2, 4, 1];
let Latency = 3;
let NumMicroOps = 7;
}
-def : InstRW<[ADLPWriteResGroup101], (instregex "^LOOP$")>;
+def : InstRW<[ADLPWriteResGroup102], (instrs LOOP)>;
-def ADLPWriteResGroup102 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
+def ADLPWriteResGroup103 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
let ResourceCycles = [4, 6, 1];
let Latency = 3;
let NumMicroOps = 11;
}
-def : InstRW<[ADLPWriteResGroup102], (instregex "^LOOPE$")>;
+def : InstRW<[ADLPWriteResGroup103], (instrs LOOPE)>;
-def ADLPWriteResGroup103 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
+def ADLPWriteResGroup104 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
let ResourceCycles = [4, 6, 1];
let Latency = 2;
let NumMicroOps = 11;
}
-def : InstRW<[ADLPWriteResGroup103], (instregex "^LOOPNE$")>;
+def : InstRW<[ADLPWriteResGroup104], (instrs LOOPNE)>;
-def ADLPWriteResGroup104 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort02_03, ADLPPort06]> {
+def ADLPWriteResGroup105 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort02_03, ADLPPort06]> {
let Latency = 7;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup104], (instregex "^LRET64$")>;
+def : InstRW<[ADLPWriteResGroup105], (instrs LRET64)>;
-def ADLPWriteResGroup105 : SchedWriteRes<[ADLPPort00, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup106 : SchedWriteRes<[ADLPPort00, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
let ResourceCycles = [1, 5, 3, 3, 1];
let Latency = 70;
let NumMicroOps = 13;
}
-def : InstRW<[ADLPWriteResGroup105], (instregex "^LSL(16|32|64)rm$")>;
+def : InstRW<[ADLPWriteResGroup106], (instregex "^LSL(16|32|64)rm$")>;
-def ADLPWriteResGroup106 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup107 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
let ResourceCycles = [1, 4, 4, 3, 2, 1];
let Latency = 63;
let NumMicroOps = 15;
}
-def : InstRW<[ADLPWriteResGroup106], (instregex "^LSL(16|32|64)rr$")>;
+def : InstRW<[ADLPWriteResGroup107], (instregex "^LSL(16|32|64)rr$")>;
-def ADLPWriteResGroup107 : SchedWriteRes<[ADLPPort00_01, ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup108 : SchedWriteRes<[ADLPPort00_01, ADLPPort02_03_11, ADLPPort05]> {
let Latency = 24;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup107], (instregex "^MMX_CVT(T?)PD2PIrm$")>;
+def : InstRW<[ADLPWriteResGroup108], (instregex "^MMX_CVT(T?)PD2PIrm$")>;
-def ADLPWriteResGroup108 : SchedWriteRes<[ADLPPort00_01, ADLPPort05]> {
+def ADLPWriteResGroup109 : SchedWriteRes<[ADLPPort00_01, ADLPPort05]> {
let Latency = 8;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup108], (instregex "^MMX_CVT(T?)PD2PIrr$")>;
+def : InstRW<[ADLPWriteResGroup109], (instregex "^MMX_CVT(T?)PD2PIrr$")>;
-def ADLPWriteResGroup109 : SchedWriteRes<[ADLPPort00_01, ADLPPort05]> {
+def ADLPWriteResGroup110 : SchedWriteRes<[ADLPPort00_01, ADLPPort05]> {
let Latency = 6;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup109], (instregex "^MMX_CVTPI2PDrr$")>;
+def : InstRW<[ADLPWriteResGroup110], (instrs MMX_CVTPI2PDrr)>;
-def ADLPWriteResGroup110 : SchedWriteRes<[ADLPPort00, ADLPPort00_01]> {
+def ADLPWriteResGroup111 : SchedWriteRes<[ADLPPort00, ADLPPort00_01]> {
let Latency = 7;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup110], (instregex "^MMX_CVTPI2PSrr$")>;
+def : InstRW<[ADLPWriteResGroup111], (instrs MMX_CVTPI2PSrr)>;
-def ADLPWriteResGroup111 : SchedWriteRes<[ADLPPort00, ADLPPort02_03_11]> {
+def ADLPWriteResGroup112 : SchedWriteRes<[ADLPPort00, ADLPPort02_03_11]> {
let Latency = 13;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup111], (instregex "^MMX_CVT(T?)PS2PIrm$")>;
+def : InstRW<[ADLPWriteResGroup112], (instregex "^MMX_CVT(T?)PS2PIrm$")>;
-def ADLPWriteResGroup112 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05]> {
+def ADLPWriteResGroup113 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05]> {
let Latency = 9;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup112], (instregex "^MMX_CVT(T?)PS2PIrr$")>;
+def : InstRW<[ADLPWriteResGroup113], (instregex "^MMX_CVT(T?)PS2PIrr$")>;
-def ADLPWriteResGroup113 : SchedWriteRes<[ADLPPort00, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup114 : SchedWriteRes<[ADLPPort00, ADLPPort04_09, ADLPPort07_08]> {
let ResourceCycles = [2, 1, 1];
let Latency = 12;
let NumMicroOps = 4;
}
-def : InstRW<[ADLPWriteResGroup113], (instregex "^MMX_MASKMOVQ((64)?)$")>;
+def : InstRW<[ADLPWriteResGroup114], (instregex "^MMX_MASKMOVQ((64)?)$")>;
-def ADLPWriteResGroup114 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup115 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
let Latency = 18;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup114], (instregex "^MMX_MOVD64mr$")>;
+def : InstRW<[ADLPWriteResGroup115], (instrs MMX_MOVD64mr)>;
-def ADLPWriteResGroup115 : SchedWriteRes<[ADLPPort02_03_11]> {
+def ADLPWriteResGroup116 : SchedWriteRes<[ADLPPort02_03_11]> {
let Latency = 8;
}
-def : InstRW<[ADLPWriteResGroup115], (instregex "^MMX_MOV(D|Q)64rm$",
+def : InstRW<[ADLPWriteResGroup116], (instregex "^MMX_MOV(D|Q)64rm$",
"^VBROADCAST(F|I)128$",
"^VBROADCASTS(D|S)Yrm$",
"^VMOV(D|SH|SL)DUPYrm$",
"^VPBROADCAST(D|Q)Yrm$")>;
-def ADLPWriteResGroup116 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort00_05]> {
+def ADLPWriteResGroup117 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort00_05]> {
let Latency = 3;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup116], (instregex "^MMX_MOVDQ2Qrr$")>;
+def : InstRW<[ADLPWriteResGroup117], (instrs MMX_MOVDQ2Qrr)>;
-def ADLPWriteResGroup117 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05]> {
+def ADLPWriteResGroup118 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05]> {
let Latency = 3;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup117], (instregex "^MMX_MOVQ2DQrr$")>;
+def : InstRW<[ADLPWriteResGroup118], (instrs MMX_MOVQ2DQrr)>;
-def ADLPWriteResGroup118 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup119 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
let ResourceCycles = [1, 2];
let Latency = 12;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup118, ReadAfterVecLd], (instregex "^MMX_PACKSS(DW|WB)rm$",
- "^MMX_PACKUSWBrm$")>;
+def : InstRW<[ADLPWriteResGroup119, ReadAfterVecLd], (instregex "^MMX_PACKSS(DW|WB)rm$")>;
+def : InstRW<[ADLPWriteResGroup119, ReadAfterVecLd], (instrs MMX_PACKUSWBrm)>;
-def ADLPWriteResGroup119 : SchedWriteRes<[ADLPPort05]> {
+def ADLPWriteResGroup120 : SchedWriteRes<[ADLPPort05]> {
let ResourceCycles = [2];
let Latency = 4;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup119], (instregex "^MMX_PACKSS(DW|WB)rr$",
- "^MMX_PACKUSWBrr$")>;
-def : InstRW<[ADLPWriteResGroup119, ReadDefault, ReadInt2Fpu], (instregex "^MMX_PINSRWrr$")>;
+def : InstRW<[ADLPWriteResGroup120], (instregex "^MMX_PACKSS(DW|WB)rr$")>;
+def : InstRW<[ADLPWriteResGroup120], (instrs MMX_PACKUSWBrr)>;
+def : InstRW<[ADLPWriteResGroup120, ReadDefault, ReadInt2Fpu], (instrs MMX_PINSRWrr)>;
-def ADLPWriteResGroup120 : SchedWriteRes<[ADLPPort00_05, ADLPPort02_03_11]> {
+def ADLPWriteResGroup121 : SchedWriteRes<[ADLPPort00_05, ADLPPort02_03_11]> {
let Latency = 9;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup120, ReadAfterVecLd], (instregex "^MMX_P(ADD|SUB)(B|D|Q|W)rm$")>;
+def : InstRW<[ADLPWriteResGroup121, ReadAfterVecLd], (instregex "^MMX_P(ADD|SUB)(B|D|Q|W)rm$")>;
-def ADLPWriteResGroup121 : SchedWriteRes<[ADLPPort00, ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup122 : SchedWriteRes<[ADLPPort00, ADLPPort02_03_11, ADLPPort05]> {
let ResourceCycles = [1, 1, 2];
let Latency = 11;
let NumMicroOps = 4;
}
-def : InstRW<[ADLPWriteResGroup121, ReadAfterVecLd], (instregex "^MMX_PH(ADD|SUB)SWrm$")>;
+def : InstRW<[ADLPWriteResGroup122, ReadAfterVecLd], (instregex "^MMX_PH(ADD|SUB)SWrm$")>;
-def ADLPWriteResGroup122 : SchedWriteRes<[ADLPPort00, ADLPPort05]> {
+def ADLPWriteResGroup123 : SchedWriteRes<[ADLPPort00, ADLPPort05]> {
let ResourceCycles = [1, 2];
let Latency = 3;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup122], (instregex "^MMX_PH(ADD|SUB)SWrr$")>;
+def : InstRW<[ADLPWriteResGroup123], (instregex "^MMX_PH(ADD|SUB)SWrr$")>;
-def ADLPWriteResGroup123 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup124 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
let Latency = 9;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup123], (instregex "^VPBROADCAST(B|W)Yrm$")>;
-def : InstRW<[ADLPWriteResGroup123, ReadAfterLd], (instregex "^MMX_PINSRWrm$")>;
-def : InstRW<[ADLPWriteResGroup123, ReadAfterVecYLd], (instregex "^VPALIGNRYrmi$")>;
+def : InstRW<[ADLPWriteResGroup124], (instregex "^VPBROADCAST(B|W)Yrm$")>;
+def : InstRW<[ADLPWriteResGroup124, ReadAfterLd], (instrs MMX_PINSRWrm)>;
+def : InstRW<[ADLPWriteResGroup124, ReadAfterVecYLd], (instrs VPALIGNRYrmi)>;
-def ADLPWriteResGroup124 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
+def ADLPWriteResGroup125 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
let Latency = 5;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup124], (instregex "^MOV16ao(16|32|64)$")>;
+def : InstRW<[ADLPWriteResGroup125], (instregex "^MOV16ao(16|32|64)$")>;
-def ADLPWriteResGroup125 : SchedWriteRes<[ADLPPort01, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup126 : SchedWriteRes<[ADLPPort01, ADLPPort04_09, ADLPPort07_08]> {
let Latency = 12;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup125], (instregex "^MOV16ms$",
- "^MOVBE32mr$",
- "^PUSH(F|G)S(16|32)$")>;
+def : InstRW<[ADLPWriteResGroup126], (instregex "^PUSH(F|G)S(16|32)$")>;
+def : InstRW<[ADLPWriteResGroup126], (instrs MOV16ms,
+ MOVBE32mr)>;
-def ADLPWriteResGroup126 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort01]> {
+def ADLPWriteResGroup127 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort01]> {
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup126], (instregex "^MOV(16|32|64)rs$",
+def : InstRW<[ADLPWriteResGroup127], (instregex "^MOV(16|32|64)rs$",
"^S(TR|LDT)16r$")>;
-def ADLPWriteResGroup127 : SchedWriteRes<[ADLPPort02_03_11]>;
-def : InstRW<[ADLPWriteResGroup127], (instregex "^MOV32ao(16|32|64)$",
- "^MOV64ao64$")>;
+def ADLPWriteResGroup128 : SchedWriteRes<[ADLPPort02_03_11]>;
+def : InstRW<[ADLPWriteResGroup128], (instregex "^MOV32ao(16|32|64)$")>;
+def : InstRW<[ADLPWriteResGroup128], (instrs MOV64ao64)>;
-def ADLPWriteResGroup128 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup129 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort04_09, ADLPPort07_08]> {
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup128], (instregex "^MOV(8|32)o(16|32)a$",
+def : InstRW<[ADLPWriteResGroup129], (instregex "^MOV(8|32)o(16|32)a$",
"^MOV(8|32|64)o64a$")>;
-def ADLPWriteResGroup129 : SchedWriteRes<[ADLPPort00_01_05_06_10]> {
+def ADLPWriteResGroup130 : SchedWriteRes<[ADLPPort00_01_05_06_10]> {
let Latency = 0;
}
-def : InstRW<[ADLPWriteResGroup129], (instregex "^MOV32rr$",
- "^MOV32rr_REV$",
- "^MOVZX(32|64)rr8$")>;
+def : InstRW<[ADLPWriteResGroup130], (instregex "^MOVZX(32|64)rr8$")>;
+def : InstRW<[ADLPWriteResGroup130], (instrs MOV32rr,
+ MOV32rr_REV)>;
-def ADLPWriteResGroup130 : SchedWriteRes<[ADLPPort02_03_11]> {
+def ADLPWriteResGroup131 : SchedWriteRes<[ADLPPort02_03_11]> {
let Latency = 5;
}
-def : InstRW<[ADLPWriteResGroup130], (instregex "^MOV64ao32$",
- "^MOVZX(32|64)rm(8|16)$")>;
+def : InstRW<[ADLPWriteResGroup131], (instrs MOV64ao32)>;
-def ADLPWriteResGroup131 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup132 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [1, 2, 4, 16, 7, 2, 2, 12, 2];
let Latency = 217;
let NumMicroOps = 48;
}
-def : InstRW<[ADLPWriteResGroup131], (instregex "^MOV64dr$")>;
+def : InstRW<[ADLPWriteResGroup132], (instrs MOV64dr)>;
-def ADLPWriteResGroup132 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup133 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
let Latency = 12;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup132], (instregex "^MOV64o32a$")>;
+def : InstRW<[ADLPWriteResGroup133], (instrs MOV64o32a)>;
-def ADLPWriteResGroup133 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort05]> {
+def ADLPWriteResGroup134 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort05]> {
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup133], (instregex "^MOV64rc$")>;
+def : InstRW<[ADLPWriteResGroup134], (instrs MOV64rc)>;
-def ADLPWriteResGroup134 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort05]> {
+def ADLPWriteResGroup135 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort05]> {
let ResourceCycles = [3, 4, 8, 4, 2, 3];
let Latency = 181;
let NumMicroOps = 24;
}
-def : InstRW<[ADLPWriteResGroup134], (instregex "^MOV64rd$")>;
+def : InstRW<[ADLPWriteResGroup135], (instrs MOV64rd)>;
-def ADLPWriteResGroup135 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
+def ADLPWriteResGroup136 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup135], (instregex "^MOV8ao(16|32|64)$")>;
+def : InstRW<[ADLPWriteResGroup136], (instregex "^MOV8ao(16|32|64)$")>;
-def ADLPWriteResGroup136 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup137 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
let Latency = 13;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup136], (instregex "^MOV8m(i|r)$")>;
+def : InstRW<[ADLPWriteResGroup137], (instregex "^MOV8m(i|r)$")>;
-def ADLPWriteResGroup137 : SchedWriteRes<[ADLPPort00_06, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup138 : SchedWriteRes<[ADLPPort00_06, ADLPPort04_09, ADLPPort07_08]> {
let Latency = 12;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup137], (instregex "^MOVBE16mr$")>;
+def : InstRW<[ADLPWriteResGroup138], (instrs MOVBE16mr)>;
-def ADLPWriteResGroup138 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort02_03_11]> {
+def ADLPWriteResGroup139 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort02_03_11]> {
let Latency = 7;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup138], (instregex "^MOVBE16rm$")>;
+def : InstRW<[ADLPWriteResGroup139], (instrs MOVBE16rm)>;
-def ADLPWriteResGroup139 : SchedWriteRes<[ADLPPort01, ADLPPort02_03_11]> {
+def ADLPWriteResGroup140 : SchedWriteRes<[ADLPPort01, ADLPPort02_03_11]> {
let Latency = 6;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup139], (instregex "^MOVBE32rm$")>;
+def : InstRW<[ADLPWriteResGroup140], (instrs MOVBE32rm)>;
-def ADLPWriteResGroup140 : SchedWriteRes<[ADLPPort00_06, ADLPPort01, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup141 : SchedWriteRes<[ADLPPort00_06, ADLPPort01, ADLPPort04_09, ADLPPort07_08]> {
let Latency = 12;
let NumMicroOps = 4;
}
-def : InstRW<[ADLPWriteResGroup140], (instregex "^MOVBE64mr$",
- "^PUSHF16$",
- "^SLDT16m$",
- "^STRm$")>;
+def : InstRW<[ADLPWriteResGroup141], (instrs MOVBE64mr,
+ PUSHF16,
+ SLDT16m,
+ STRm)>;
-def ADLPWriteResGroup141 : SchedWriteRes<[ADLPPort00_06, ADLPPort01, ADLPPort02_03_11]> {
+def ADLPWriteResGroup142 : SchedWriteRes<[ADLPPort00_06, ADLPPort01, ADLPPort02_03_11]> {
let Latency = 7;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup141], (instregex "^MOVBE64rm$")>;
+def : InstRW<[ADLPWriteResGroup142], (instrs MOVBE64rm)>;
-def ADLPWriteResGroup142 : SchedWriteRes<[ADLPPort00_06, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup143 : SchedWriteRes<[ADLPPort00_06, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
let NumMicroOps = 4;
}
-def : InstRW<[ADLPWriteResGroup142], (instregex "^MOVDIR64B(16|32|64)$")>;
+def : InstRW<[ADLPWriteResGroup143], (instregex "^MOVDIR64B(16|32|64)$")>;
-def ADLPWriteResGroup143 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup144 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
let Latency = 511;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup143], (instregex "^MOVDIRI32$")>;
+def : InstRW<[ADLPWriteResGroup144], (instrs MOVDIRI32)>;
-def ADLPWriteResGroup144 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup145 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
let Latency = 514;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup144], (instregex "^MOVDIRI64$")>;
+def : InstRW<[ADLPWriteResGroup145], (instrs MOVDIRI64)>;
-def ADLPWriteResGroup145 : SchedWriteRes<[ADLPPort01_05, ADLPPort02_03_11]> {
+def ADLPWriteResGroup146 : SchedWriteRes<[ADLPPort01_05, ADLPPort02_03_11]> {
let Latency = 8;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup145, ReadAfterVecXLd], (instregex "^(V?)MOVLP(D|S)rm$",
+def : InstRW<[ADLPWriteResGroup146, ReadAfterVecXLd], (instregex "^(V?)MOVLP(D|S)rm$",
"^(V?)SHUFP(D|S)rmi$")>;
-def ADLPWriteResGroup146 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup147 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
let Latency = 512;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup146], (instregex "^MOVNTDQmr$")>;
+def : InstRW<[ADLPWriteResGroup147], (instrs MOVNTDQmr)>;
-def ADLPWriteResGroup147 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup148 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
let Latency = 518;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup147], (instregex "^MOVNTImr$")>;
+def : InstRW<[ADLPWriteResGroup148], (instrs MOVNTImr)>;
-def ADLPWriteResGroup148 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup149 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
let ResourceCycles = [4, 1, 1, 1];
let Latency = 8;
let NumMicroOps = 7;
}
-def : InstRW<[ADLPWriteResGroup148], (instregex "^MOVSB$")>;
+def : InstRW<[ADLPWriteResGroup149], (instrs MOVSB)>;
-def ADLPWriteResGroup149 : SchedWriteRes<[ADLPPort00_01_05]>;
-def : InstRW<[ADLPWriteResGroup149], (instregex "^(V?)MOVS(D|S)rr$",
+def ADLPWriteResGroup150 : SchedWriteRes<[ADLPPort00_01_05]>;
+def : InstRW<[ADLPWriteResGroup150], (instregex "^(V?)MOVS(D|S)rr$",
"^(V?)MOVS(D|S)rr_REV$",
"^(V?)P(ADD|SUB)(B|D|Q|W)rr$",
- "^VP(ADD|SUB)(B|D|Q|W)Yrr$",
- "^VPBLENDDrri$")>;
+ "^VP(ADD|SUB)(B|D|Q|W)Yrr$")>;
+def : InstRW<[ADLPWriteResGroup150], (instrs VPBLENDDrri)>;
-def ADLPWriteResGroup150 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup151 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
let ResourceCycles = [4, 1, 1, 1];
let Latency = 7;
let NumMicroOps = 7;
}
-def : InstRW<[ADLPWriteResGroup150], (instregex "^MOVS(L|Q|W)$")>;
+def : InstRW<[ADLPWriteResGroup151], (instregex "^MOVS(L|Q|W)$")>;
-def ADLPWriteResGroup151 : SchedWriteRes<[ADLPPort01_05_10, ADLPPort02_03_11]> {
+def ADLPWriteResGroup152 : SchedWriteRes<[ADLPPort01_05_10, ADLPPort02_03_11]> {
let Latency = 6;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup151], (instregex "^MOVSX16rm8$")>;
+def : InstRW<[ADLPWriteResGroup152], (instrs MOVSX16rm8)>;
-def ADLPWriteResGroup152 : SchedWriteRes<[ADLPPort01_05_10]>;
-def : InstRW<[ADLPWriteResGroup152], (instregex "^MOVSX(16|32|64)rr8$",
- "^MOVSX(32|64)rr16$",
- "^MOVSX64rr32$")>;
+def ADLPWriteResGroup153 : SchedWriteRes<[ADLPPort01_05_10]>;
+def : InstRW<[ADLPWriteResGroup153], (instregex "^MOVSX(16|32|64)rr8$",
+ "^MOVSX(32|64)rr16$")>;
+def : InstRW<[ADLPWriteResGroup153], (instrs MOVSX64rr32)>;
-def ADLPWriteResGroup153 : SchedWriteRes<[ADLPPort02_03_11]> {
+def ADLPWriteResGroup154 : SchedWriteRes<[ADLPPort02_03_11]> {
let Latency = 6;
}
-def : InstRW<[ADLPWriteResGroup153], (instregex "^MOVSX(32|64)rm(8|16)$",
- "^MOVSX64rm32$")>;
+def : InstRW<[ADLPWriteResGroup154], (instregex "^MOVSX(32|64)rm(8|16)$")>;
+def : InstRW<[ADLPWriteResGroup154], (instrs MOVSX64rm32)>;
-def ADLPWriteResGroup154 : SchedWriteRes<[ADLPPort00_01]> {
+def ADLPWriteResGroup155 : SchedWriteRes<[ADLPPort00_01]> {
let Latency = 4;
}
-def : InstRW<[ADLPWriteResGroup154], (instregex "^(V?)MULSSrr_Int$")>;
+def : InstRW<[ADLPWriteResGroup155], (instregex "^(V?)MULSSrr_Int$")>;
-def ADLPWriteResGroup155 : SchedWriteRes<[ADLPPort00, ADLPPort02_03]> {
+def ADLPWriteResGroup156 : SchedWriteRes<[ADLPPort00, ADLPPort02_03]> {
let Latency = 11;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup155], (instregex "^MUL_F(32|64)m$")>;
+def : InstRW<[ADLPWriteResGroup156], (instregex "^MUL_F(32|64)m$")>;
-def ADLPWriteResGroup156 : SchedWriteRes<[ADLPPort00, ADLPPort02_03, ADLPPort05]> {
+def ADLPWriteResGroup157 : SchedWriteRes<[ADLPPort00, ADLPPort02_03, ADLPPort05]> {
let Latency = 14;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup156], (instregex "^MUL_FI(16|32)m$")>;
+def : InstRW<[ADLPWriteResGroup157], (instregex "^MUL_FI(16|32)m$")>;
-def ADLPWriteResGroup157 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort05, ADLPPort06]> {
+def ADLPWriteResGroup158 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort05, ADLPPort06]> {
let ResourceCycles = [7, 1, 2];
let Latency = 20;
let NumMicroOps = 10;
}
-def : InstRW<[ADLPWriteResGroup157], (instregex "^MWAITrr$")>;
+def : InstRW<[ADLPWriteResGroup158], (instrs MWAITrr)>;
-def ADLPWriteResGroup158 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup159 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [6, 4, 1, 28, 15, 7, 1, 16, 1];
let Latency = 35;
let NumMicroOps = 79;
}
-def : InstRW<[ADLPWriteResGroup158], (instregex "^OUT16ir$")>;
+def : InstRW<[ADLPWriteResGroup159], (instrs OUT16ir)>;
-def ADLPWriteResGroup159 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup160 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [6, 6, 27, 15, 7, 1, 16, 1];
let Latency = 35;
let NumMicroOps = 79;
}
-def : InstRW<[ADLPWriteResGroup159], (instregex "^OUT16rr$")>;
+def : InstRW<[ADLPWriteResGroup160], (instrs OUT16rr)>;
-def ADLPWriteResGroup160 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup161 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [6, 4, 1, 30, 15, 9, 1, 18, 1];
let Latency = 35;
let NumMicroOps = 85;
}
-def : InstRW<[ADLPWriteResGroup160], (instregex "^OUT32ir$")>;
+def : InstRW<[ADLPWriteResGroup161], (instrs OUT32ir)>;
-def ADLPWriteResGroup161 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup162 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [6, 6, 29, 15, 9, 1, 18, 1];
let Latency = 35;
let NumMicroOps = 85;
}
-def : InstRW<[ADLPWriteResGroup161], (instregex "^OUT32rr$")>;
+def : InstRW<[ADLPWriteResGroup162], (instrs OUT32rr)>;
-def ADLPWriteResGroup162 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup163 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [5, 5, 1, 25, 15, 5, 1, 15, 1];
let Latency = 35;
let NumMicroOps = 73;
}
-def : InstRW<[ADLPWriteResGroup162], (instregex "^OUT8ir$")>;
+def : InstRW<[ADLPWriteResGroup163], (instrs OUT8ir)>;
-def ADLPWriteResGroup163 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup164 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [5, 5, 26, 15, 5, 1, 15, 1];
let Latency = 35;
let NumMicroOps = 73;
}
-def : InstRW<[ADLPWriteResGroup163], (instregex "^OUT8rr$")>;
+def : InstRW<[ADLPWriteResGroup164], (instrs OUT8rr)>;
-def ADLPWriteResGroup164 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup165 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [7, 6, 25, 16, 7, 1, 17, 1];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 80;
}
-def : InstRW<[ADLPWriteResGroup164], (instregex "^OUTSB$")>;
+def : InstRW<[ADLPWriteResGroup165], (instrs OUTSB)>;
-def ADLPWriteResGroup165 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup166 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [7, 6, 28, 16, 10, 1, 20, 1];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 89;
}
-def : InstRW<[ADLPWriteResGroup165], (instregex "^OUTSL$")>;
+def : InstRW<[ADLPWriteResGroup166], (instrs OUTSL)>;
-def ADLPWriteResGroup166 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup167 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [6, 1, 5, 27, 16, 8, 1, 18, 1];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 83;
}
-def : InstRW<[ADLPWriteResGroup166], (instregex "^OUTSW$")>;
+def : InstRW<[ADLPWriteResGroup167], (instrs OUTSW)>;
-def ADLPWriteResGroup167 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup168 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
let Latency = 10;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup167, ReadAfterVecXLd], (instregex "^(V?)PACK(S|U)S(DW|WB)rm$",
+def : InstRW<[ADLPWriteResGroup168, ReadAfterVecXLd], (instregex "^(V?)PACK(S|U)S(DW|WB)rm$",
"^(V?)PCMPGTQrm$")>;
-def ADLPWriteResGroup168 : SchedWriteRes<[ADLPPort05]> {
+def ADLPWriteResGroup169 : SchedWriteRes<[ADLPPort05]> {
let Latency = 3;
}
-def : InstRW<[ADLPWriteResGroup168], (instregex "^(V?)PACK(S|U)S(DW|WB)rr$",
+def : InstRW<[ADLPWriteResGroup169], (instregex "^(V?)PACK(S|U)S(DW|WB)rr$",
"^(V?)PCMPGTQrr$",
- "^VPACK(S|U)S(DW|WB)Yrr$",
- "^VPCMPGTQYrr$")>;
+ "^VPACK(S|U)S(DW|WB)Yrr$")>;
+def : InstRW<[ADLPWriteResGroup169], (instrs VPCMPGTQYrr)>;
-def ADLPWriteResGroup169 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort02_03_11]> {
+def ADLPWriteResGroup170 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort02_03_11]> {
let Latency = 8;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup169, ReadAfterVecXLd], (instregex "^(V?)P(ADD|SUB)(B|D|Q|W)rm$",
- "^VPBLENDDrmi$")>;
+def : InstRW<[ADLPWriteResGroup170, ReadAfterVecXLd], (instregex "^(V?)P(ADD|SUB)(B|D|Q|W)rm$")>;
+def : InstRW<[ADLPWriteResGroup170, ReadAfterVecXLd], (instrs VPBLENDDrmi)>;
-def ADLPWriteResGroup170 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup171 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
let Latency = 8;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup170], (instregex "^VPBROADCAST(B|W)rm$")>;
-def : InstRW<[ADLPWriteResGroup170, ReadAfterVecXLd], (instregex "^(V?)PALIGNRrmi$")>;
+def : InstRW<[ADLPWriteResGroup171], (instregex "^VPBROADCAST(B|W)rm$")>;
+def : InstRW<[ADLPWriteResGroup171, ReadAfterVecXLd], (instregex "^(V?)PALIGNRrmi$")>;
-def ADLPWriteResGroup171 : SchedWriteRes<[ADLPPort05]>;
-def : InstRW<[ADLPWriteResGroup171], (instregex "^(V?)PALIGNRrri$",
- "^VPALIGNRYrri$",
+def ADLPWriteResGroup172 : SchedWriteRes<[ADLPPort05]>;
+def : InstRW<[ADLPWriteResGroup172], (instregex "^(V?)PALIGNRrri$",
"^VPBROADCAST(B|D|Q|W)rr$")>;
+def : InstRW<[ADLPWriteResGroup172], (instrs VPALIGNRYrri)>;
-def ADLPWriteResGroup172 : SchedWriteRes<[ADLPPort00_06, ADLPPort05]> {
+def ADLPWriteResGroup173 : SchedWriteRes<[ADLPPort00_06, ADLPPort05]> {
let Latency = 4;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup172], (instregex "^PAUSE$")>;
+def : InstRW<[ADLPWriteResGroup173], (instrs PAUSE)>;
-def ADLPWriteResGroup173 : SchedWriteRes<[ADLPPort01, ADLPPort02_03_11]> {
+def ADLPWriteResGroup174 : SchedWriteRes<[ADLPPort01, ADLPPort02_03_11]> {
let Latency = 8;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup173, ReadAfterLd], (instregex "^P(DEP|EXT)(32|64)rm$")>;
+def : InstRW<[ADLPWriteResGroup174, ReadAfterLd], (instregex "^P(DEP|EXT)(32|64)rm$")>;
-def ADLPWriteResGroup174 : SchedWriteRes<[ADLPPort01_05, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup175 : SchedWriteRes<[ADLPPort01_05, ADLPPort04_09, ADLPPort07_08]> {
let Latency = 12;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup174], (instregex "^(V?)PEXTR(D|Q)mr$")>;
+def : InstRW<[ADLPWriteResGroup175], (instregex "^(V?)PEXTR(D|Q)mr$")>;
-def ADLPWriteResGroup175 : SchedWriteRes<[ADLPPort00_01, ADLPPort01_05, ADLPPort02_03_11]> {
+def ADLPWriteResGroup176 : SchedWriteRes<[ADLPPort00_01, ADLPPort01_05, ADLPPort02_03_11]> {
let ResourceCycles = [1, 2, 1];
let Latency = 9;
let NumMicroOps = 4;
}
-def : InstRW<[ADLPWriteResGroup175, ReadAfterVecXLd], (instregex "^(V?)PH(ADD|SUB)SWrm$")>;
+def : InstRW<[ADLPWriteResGroup176, ReadAfterVecXLd], (instregex "^(V?)PH(ADD|SUB)SWrm$")>;
-def ADLPWriteResGroup176 : SchedWriteRes<[ADLPPort00_01, ADLPPort01_05]> {
+def ADLPWriteResGroup177 : SchedWriteRes<[ADLPPort00_01, ADLPPort01_05]> {
let ResourceCycles = [1, 2];
let Latency = 2;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup176], (instregex "^(V?)PH(ADD|SUB)SWrr$",
+def : InstRW<[ADLPWriteResGroup177], (instregex "^(V?)PH(ADD|SUB)SWrr$",
"^VPH(ADD|SUB)SWYrr$")>;
-def ADLPWriteResGroup177 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup178 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
let Latency = 12;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup177], (instregex "^POP(16|32|64)rmm$",
+def : InstRW<[ADLPWriteResGroup178], (instregex "^POP(16|32|64)rmm$",
"^PUSH(16|32)rmm$")>;
-def ADLPWriteResGroup178 : SchedWriteRes<[ADLPPort02_03]> {
+def ADLPWriteResGroup179 : SchedWriteRes<[ADLPPort02_03]> {
let Latency = 5;
}
-def : InstRW<[ADLPWriteResGroup178], (instregex "^POPA(16|32)$",
- "^POPF32$")>;
+def : InstRW<[ADLPWriteResGroup179], (instregex "^POPA(16|32)$",
+ "^PREFETCHIT(0|1)$")>;
+def : InstRW<[ADLPWriteResGroup179], (instrs POPF32)>;
-def ADLPWriteResGroup179 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11]> {
+def ADLPWriteResGroup180 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11]> {
let ResourceCycles = [6, 2, 1, 1];
let Latency = 5;
let NumMicroOps = 10;
}
-def : InstRW<[ADLPWriteResGroup179], (instregex "^POPF16$")>;
+def : InstRW<[ADLPWriteResGroup180], (instrs POPF16)>;
-def ADLPWriteResGroup180 : SchedWriteRes<[ADLPPort00_06, ADLPPort01, ADLPPort02_03_11]> {
+def ADLPWriteResGroup181 : SchedWriteRes<[ADLPPort00_06, ADLPPort01, ADLPPort02_03_11]> {
let ResourceCycles = [2, 1, 1];
let Latency = 5;
let NumMicroOps = 7;
}
-def : InstRW<[ADLPWriteResGroup180], (instregex "^POPF64$")>;
+def : InstRW<[ADLPWriteResGroup181], (instrs POPF64)>;
-def ADLPWriteResGroup181 : SchedWriteRes<[ADLPPort02_03_11]> {
+def ADLPWriteResGroup182 : SchedWriteRes<[ADLPPort02_03_11]> {
let Latency = 0;
}
-def : InstRW<[ADLPWriteResGroup181], (instregex "^PREFETCH(T0|T1|T2|NTA)$")>;
+def : InstRW<[ADLPWriteResGroup182], (instregex "^PREFETCH(T0|T1|T2|NTA)$")>;
-def ADLPWriteResGroup182 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11, ADLPPort06]> {
+def ADLPWriteResGroup183 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11, ADLPPort06]> {
let ResourceCycles = [1, 1, 2];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 4;
}
-def : InstRW<[ADLPWriteResGroup182], (instregex "^PTWRITE((64)?)m$")>;
+def : InstRW<[ADLPWriteResGroup183], (instregex "^PTWRITE((64)?)m$")>;
-def ADLPWriteResGroup183 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort06]> {
+def ADLPWriteResGroup184 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort06]> {
let ResourceCycles = [1, 2];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup183], (instregex "^PTWRITE64r$")>;
+def : InstRW<[ADLPWriteResGroup184], (instrs PTWRITE64r)>;
-def ADLPWriteResGroup184 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort06]> {
+def ADLPWriteResGroup185 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort06]> {
let ResourceCycles = [2, 2];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 4;
}
-def : InstRW<[ADLPWriteResGroup184], (instregex "^PTWRITEr$")>;
+def : InstRW<[ADLPWriteResGroup185], (instrs PTWRITEr)>;
-def ADLPWriteResGroup185 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup186 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup185], (instregex "^PUSH64r$")>;
+def : InstRW<[ADLPWriteResGroup186], (instrs PUSH64r)>;
-def ADLPWriteResGroup186 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup187 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup186], (instregex "^PUSH64rmm$")>;
+def : InstRW<[ADLPWriteResGroup187], (instrs PUSH64rmm)>;
-def ADLPWriteResGroup187 : SchedWriteRes<[ADLPPort02_03_07, ADLPPort04]>;
-def : InstRW<[ADLPWriteResGroup187], (instregex "^PUSHA(16|32)$",
- "^PUSHF32$",
+def ADLPWriteResGroup188 : SchedWriteRes<[ADLPPort02_03_07, ADLPPort04]>;
+def : InstRW<[ADLPWriteResGroup188], (instregex "^PUSHA(16|32)$",
"^ST_F(32|64)m$")>;
+def : InstRW<[ADLPWriteResGroup188], (instrs PUSHF32)>;
-def ADLPWriteResGroup188 : SchedWriteRes<[ADLPPort00_06, ADLPPort01, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup189 : SchedWriteRes<[ADLPPort00_06, ADLPPort01, ADLPPort04_09, ADLPPort07_08]> {
let Latency = 4;
let NumMicroOps = 4;
}
-def : InstRW<[ADLPWriteResGroup188], (instregex "^PUSHF64$")>;
+def : InstRW<[ADLPWriteResGroup189], (instrs PUSHF64)>;
-def ADLPWriteResGroup189 : SchedWriteRes<[ADLPPort01, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup190 : SchedWriteRes<[ADLPPort01, ADLPPort04_09, ADLPPort07_08]> {
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup189], (instregex "^PUSH(F|G)S64$")>;
+def : InstRW<[ADLPWriteResGroup190], (instregex "^PUSH(F|G)S64$")>;
-def ADLPWriteResGroup190 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
+def ADLPWriteResGroup191 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
let ResourceCycles = [2, 3, 2];
let Latency = 8;
let NumMicroOps = 7;
}
-def : InstRW<[ADLPWriteResGroup190], (instregex "^RC(L|R)(16|32|64)rCL$")>;
+def : InstRW<[ADLPWriteResGroup191], (instregex "^RC(L|R)(16|32|64)rCL$")>;
-def ADLPWriteResGroup191 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06]> {
+def ADLPWriteResGroup192 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06]> {
let ResourceCycles = [1, 2];
let Latency = 13;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup191, WriteRMW], (instregex "^RC(L|R)8m(1|i)$")>;
+def : InstRW<[ADLPWriteResGroup192, WriteRMW], (instregex "^RC(L|R)8m(1|i)$")>;
-def ADLPWriteResGroup192 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
+def ADLPWriteResGroup193 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
let ResourceCycles = [1, 5, 2];
let Latency = 20;
let NumMicroOps = 8;
}
-def : InstRW<[ADLPWriteResGroup192, WriteRMW], (instregex "^RCL8mCL$")>;
+def : InstRW<[ADLPWriteResGroup193, WriteRMW], (instrs RCL8mCL)>;
-def ADLPWriteResGroup193 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
+def ADLPWriteResGroup194 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
let ResourceCycles = [2, 5, 2];
let Latency = 7;
let NumMicroOps = 9;
}
-def : InstRW<[ADLPWriteResGroup193], (instregex "^RCL8rCL$")>;
+def : InstRW<[ADLPWriteResGroup194], (instrs RCL8rCL)>;
-def ADLPWriteResGroup194 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
+def ADLPWriteResGroup195 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
let ResourceCycles = [2, 4, 3];
let Latency = 20;
let NumMicroOps = 9;
}
-def : InstRW<[ADLPWriteResGroup194, WriteRMW], (instregex "^RCR8mCL$")>;
+def : InstRW<[ADLPWriteResGroup195, WriteRMW], (instrs RCR8mCL)>;
-def ADLPWriteResGroup195 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
+def ADLPWriteResGroup196 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
let ResourceCycles = [3, 4, 3];
let Latency = 9;
let NumMicroOps = 10;
}
-def : InstRW<[ADLPWriteResGroup195], (instregex "^RCR8rCL$")>;
+def : InstRW<[ADLPWriteResGroup196], (instrs RCR8rCL)>;
-def ADLPWriteResGroup196 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_05, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort01_05_10, ADLPPort05]> {
+def ADLPWriteResGroup197 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_05, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort01_05_10, ADLPPort05]> {
let ResourceCycles = [1, 6, 1, 10, 20, 8, 5, 1, 2];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 54;
}
-def : InstRW<[ADLPWriteResGroup196], (instregex "^RDMSR$")>;
+def : InstRW<[ADLPWriteResGroup197], (instrs RDMSR)>;
-def ADLPWriteResGroup197 : SchedWriteRes<[ADLPPort01]> {
+def ADLPWriteResGroup198 : SchedWriteRes<[ADLPPort01]> {
let Latency = AlderlakePModel.MaxLatency;
}
-def : InstRW<[ADLPWriteResGroup197], (instregex "^RDPID64$")>;
+def : InstRW<[ADLPWriteResGroup198], (instrs RDPID64)>;
-def ADLPWriteResGroup198 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
+def ADLPWriteResGroup199 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup198], (instregex "^RDPKRUr$")>;
+def : InstRW<[ADLPWriteResGroup199], (instrs RDPKRUr)>;
-def ADLPWriteResGroup199 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort05]> {
+def ADLPWriteResGroup200 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort05]> {
let ResourceCycles = [9, 6, 2, 1];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 18;
}
-def : InstRW<[ADLPWriteResGroup199], (instregex "^RDPMC$")>;
+def : InstRW<[ADLPWriteResGroup200], (instrs RDPMC)>;
-def ADLPWriteResGroup200 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup201 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort05]> {
let ResourceCycles = [2, 3, 2, 5, 7, 3, 1, 2];
let Latency = 1386;
let NumMicroOps = 25;
}
-def : InstRW<[ADLPWriteResGroup200], (instregex "^RDRAND16r$")>;
+def : InstRW<[ADLPWriteResGroup201], (instrs RDRAND16r)>;
-def ADLPWriteResGroup201 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup202 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort05]> {
let ResourceCycles = [2, 3, 2, 5, 7, 3, 1, 2];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 25;
}
-def : InstRW<[ADLPWriteResGroup201], (instregex "^RDRAND(32|64)r$")>;
+def : InstRW<[ADLPWriteResGroup202], (instregex "^RDRAND(32|64)r$")>;
-def ADLPWriteResGroup202 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup203 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
let ResourceCycles = [2, 3, 3, 5, 7, 1, 4];
let Latency = 1381;
let NumMicroOps = 25;
}
-def : InstRW<[ADLPWriteResGroup202], (instregex "^RDSEED16r$")>;
+def : InstRW<[ADLPWriteResGroup203], (instrs RDSEED16r)>;
-def ADLPWriteResGroup203 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup204 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
let ResourceCycles = [2, 3, 3, 5, 7, 1, 4];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 25;
}
-def : InstRW<[ADLPWriteResGroup203], (instregex "^RDSEED(32|64)r$")>;
+def : InstRW<[ADLPWriteResGroup204], (instregex "^RDSEED(32|64)r$")>;
-def ADLPWriteResGroup204 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort05]> {
+def ADLPWriteResGroup205 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort05]> {
let ResourceCycles = [5, 6, 3, 1];
let Latency = 18;
let NumMicroOps = 15;
}
-def : InstRW<[ADLPWriteResGroup204], (instregex "^RDTSC$")>;
+def : InstRW<[ADLPWriteResGroup205], (instrs RDTSC)>;
-def ADLPWriteResGroup205 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort05]> {
+def ADLPWriteResGroup206 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort05]> {
let ResourceCycles = [2, 2, 1, 2, 7, 4, 3];
let Latency = 42;
let NumMicroOps = 21;
}
-def : InstRW<[ADLPWriteResGroup205], (instregex "^RDTSCP$")>;
+def : InstRW<[ADLPWriteResGroup206], (instrs RDTSCP)>;
-def ADLPWriteResGroup206 : SchedWriteRes<[ADLPPort00_06, ADLPPort02_03_11]> {
+def ADLPWriteResGroup207 : SchedWriteRes<[ADLPPort00_06, ADLPPort02_03_11]> {
let Latency = 7;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup206], (instregex "^RET64$")>;
+def : InstRW<[ADLPWriteResGroup207], (instrs RET64)>;
-def ADLPWriteResGroup207 : SchedWriteRes<[ADLPPort00_06, ADLPPort02_03_11]> {
+def ADLPWriteResGroup208 : SchedWriteRes<[ADLPPort00_06, ADLPPort02_03_11]> {
let ResourceCycles = [2, 1];
let Latency = 6;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup207], (instregex "^RETI(16|32|64)$")>;
+def : InstRW<[ADLPWriteResGroup208], (instregex "^RETI(16|32|64)$")>;
-def ADLPWriteResGroup208 : SchedWriteRes<[]>;
-def : InstRW<[ADLPWriteResGroup208], (instregex "^REX64_PREFIX$")>;
+def ADLPWriteResGroup209 : SchedWriteRes<[]>;
+def : InstRW<[ADLPWriteResGroup209], (instrs REX64_PREFIX)>;
-def ADLPWriteResGroup209 : SchedWriteRes<[ADLPPort00_06]> {
+def ADLPWriteResGroup210 : SchedWriteRes<[ADLPPort00_06]> {
let ResourceCycles = [2];
let Latency = 12;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup209, WriteRMW], (instregex "^RO(L|R)(16|32|64)m(1|i|CL)$")>;
+def : InstRW<[ADLPWriteResGroup210, WriteRMW], (instregex "^RO(L|R)(16|32|64)m(1|i|CL)$")>;
-def ADLPWriteResGroup210 : SchedWriteRes<[ADLPPort00_06]> {
+def ADLPWriteResGroup211 : SchedWriteRes<[ADLPPort00_06]> {
let ResourceCycles = [2];
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup210], (instregex "^RO(L|R)(8|16|32|64)r(1|i)$")>;
+def : InstRW<[ADLPWriteResGroup211], (instregex "^RO(L|R)(8|16|32|64)r(1|i)$")>;
-def ADLPWriteResGroup211 : SchedWriteRes<[ADLPPort00_06]> {
+def ADLPWriteResGroup212 : SchedWriteRes<[ADLPPort00_06]> {
let ResourceCycles = [2];
let Latency = 13;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup211, WriteRMW], (instregex "^RO(L|R)8m(1|i)$",
+def : InstRW<[ADLPWriteResGroup212, WriteRMW], (instregex "^RO(L|R)8m(1|i)$",
"^(ROL|SAR|SHR)8mCL$",
"^(ROR|SHL)8mCL$")>;
-def ADLPWriteResGroup212 : SchedWriteRes<[ADLPPort00_06]> {
+def ADLPWriteResGroup213 : SchedWriteRes<[ADLPPort00_06]> {
let ResourceCycles = [2];
let Latency = 4;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup212], (instregex "^SAHF$")>;
+def : InstRW<[ADLPWriteResGroup213], (instrs SAHF)>;
-def ADLPWriteResGroup213 : SchedWriteRes<[ADLPPort00_06]> {
+def ADLPWriteResGroup214 : SchedWriteRes<[ADLPPort00_06]> {
let Latency = 13;
}
-def : InstRW<[ADLPWriteResGroup213, WriteRMW], (instregex "^S(A|H)R8m(1|i)$",
+def : InstRW<[ADLPWriteResGroup214, WriteRMW], (instregex "^S(A|H)R8m(1|i)$",
"^SHL8m(1|i)$")>;
-def ADLPWriteResGroup214 : SchedWriteRes<[ADLPPort00_06, ADLPPort02_03_11]> {
+def ADLPWriteResGroup215 : SchedWriteRes<[ADLPPort00_06, ADLPPort02_03_11]> {
let Latency = 8;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup214, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^S(A|H)RX(32|64)rm$",
+def : InstRW<[ADLPWriteResGroup215, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^S(A|H)RX(32|64)rm$",
"^SHLX(32|64)rm$")>;
-def ADLPWriteResGroup215 : SchedWriteRes<[ADLPPort00_06]> {
+def ADLPWriteResGroup216 : SchedWriteRes<[ADLPPort00_06]> {
let Latency = 3;
}
-def : InstRW<[ADLPWriteResGroup215], (instregex "^S(A|H)RX(32|64)rr$",
+def : InstRW<[ADLPWriteResGroup216], (instregex "^S(A|H)RX(32|64)rr$",
"^SHLX(32|64)rr$")>;
-def ADLPWriteResGroup216 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup217 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort04_09, ADLPPort07_08]> {
let ResourceCycles = [2, 2, 1, 1, 1];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 7;
}
-def : InstRW<[ADLPWriteResGroup216], (instregex "^SERIALIZE$")>;
+def : InstRW<[ADLPWriteResGroup217], (instrs SERIALIZE)>;
-def ADLPWriteResGroup217 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup218 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
let Latency = 2;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup217], (instregex "^SFENCE$")>;
+def : InstRW<[ADLPWriteResGroup218], (instrs SFENCE)>;
-def ADLPWriteResGroup218 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort01, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup219 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort01, ADLPPort04_09, ADLPPort07_08]> {
let ResourceCycles = [1, 2, 2, 2];
let Latency = 21;
let NumMicroOps = 7;
}
-def : InstRW<[ADLPWriteResGroup218], (instregex "^S(G|I)DT64m$")>;
+def : InstRW<[ADLPWriteResGroup219], (instregex "^S(G|I)DT64m$")>;
-def ADLPWriteResGroup219 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup220 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort02_03_11, ADLPPort05]> {
let Latency = 9;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup219, ReadAfterVecXLd], (instregex "^SHA1MSG1rm$")>;
+def : InstRW<[ADLPWriteResGroup220, ReadAfterVecXLd], (instrs SHA1MSG1rm)>;
-def ADLPWriteResGroup220 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort05]> {
+def ADLPWriteResGroup221 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort05]> {
let Latency = 2;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup220], (instregex "^SHA1MSG1rr$")>;
+def : InstRW<[ADLPWriteResGroup221], (instrs SHA1MSG1rr)>;
-def ADLPWriteResGroup221 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_06, ADLPPort01_05, ADLPPort02_03_11]> {
+def ADLPWriteResGroup222 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_06, ADLPPort01_05, ADLPPort02_03_11]> {
let ResourceCycles = [2, 2, 1, 2, 1];
let Latency = 13;
let NumMicroOps = 8;
}
-def : InstRW<[ADLPWriteResGroup221, ReadAfterVecXLd], (instregex "^SHA1MSG2rm$")>;
+def : InstRW<[ADLPWriteResGroup222, ReadAfterVecXLd], (instrs SHA1MSG2rm)>;
-def ADLPWriteResGroup222 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_06, ADLPPort01_05]> {
+def ADLPWriteResGroup223 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_06, ADLPPort01_05]> {
let ResourceCycles = [2, 2, 1, 2];
let Latency = 6;
let NumMicroOps = 7;
}
-def : InstRW<[ADLPWriteResGroup222], (instregex "^SHA1MSG2rr$")>;
+def : InstRW<[ADLPWriteResGroup223], (instrs SHA1MSG2rr)>;
-def ADLPWriteResGroup223 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort01_05, ADLPPort02_03_11]> {
+def ADLPWriteResGroup224 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort01_05, ADLPPort02_03_11]> {
let Latency = 8;
let NumMicroOps = 4;
}
-def : InstRW<[ADLPWriteResGroup223, ReadAfterVecXLd], (instregex "^SHA1NEXTErm$")>;
+def : InstRW<[ADLPWriteResGroup224, ReadAfterVecXLd], (instrs SHA1NEXTErm)>;
-def ADLPWriteResGroup224 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort01_05]> {
+def ADLPWriteResGroup225 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort01_05]> {
let Latency = 3;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup224], (instregex "^SHA1NEXTErr$")>;
+def : InstRW<[ADLPWriteResGroup225], (instrs SHA1NEXTErr)>;
-def ADLPWriteResGroup225 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup226 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
let Latency = 13;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup225, ReadAfterVecXLd], (instregex "^SHA1RNDS4rmi$",
- "^SHA256RNDS2rm$")>;
+def : InstRW<[ADLPWriteResGroup226, ReadAfterVecXLd], (instrs SHA1RNDS4rmi,
+ SHA256RNDS2rm)>;
-def ADLPWriteResGroup226 : SchedWriteRes<[ADLPPort05]> {
+def ADLPWriteResGroup227 : SchedWriteRes<[ADLPPort05]> {
let Latency = 6;
}
-def : InstRW<[ADLPWriteResGroup226], (instregex "^SHA1RNDS4rri$",
- "^SHA256RNDS2rr$")>;
+def : InstRW<[ADLPWriteResGroup227], (instrs SHA1RNDS4rri,
+ SHA256RNDS2rr)>;
-def ADLPWriteResGroup227 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_06, ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup228 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_06, ADLPPort02_03_11, ADLPPort05]> {
let ResourceCycles = [3, 2, 1, 1, 1];
let Latency = 12;
let NumMicroOps = 8;
}
-def : InstRW<[ADLPWriteResGroup227, ReadAfterVecXLd], (instregex "^SHA256MSG1rm$")>;
+def : InstRW<[ADLPWriteResGroup228, ReadAfterVecXLd], (instrs SHA256MSG1rm)>;
-def ADLPWriteResGroup228 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_06, ADLPPort05]> {
+def ADLPWriteResGroup229 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_06, ADLPPort05]> {
let ResourceCycles = [3, 2, 1, 1];
let Latency = 5;
let NumMicroOps = 7;
}
-def : InstRW<[ADLPWriteResGroup228], (instregex "^SHA256MSG1rr$")>;
+def : InstRW<[ADLPWriteResGroup229], (instrs SHA256MSG1rr)>;
-def ADLPWriteResGroup229 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup230 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
let ResourceCycles = [1, 2];
let Latency = 13;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup229, ReadAfterVecXLd], (instregex "^SHA256MSG2rm$")>;
+def : InstRW<[ADLPWriteResGroup230, ReadAfterVecXLd], (instrs SHA256MSG2rm)>;
-def ADLPWriteResGroup230 : SchedWriteRes<[ADLPPort05]> {
+def ADLPWriteResGroup231 : SchedWriteRes<[ADLPPort05]> {
let ResourceCycles = [2];
let Latency = 6;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup230], (instregex "^SHA256MSG2rr$")>;
+def : InstRW<[ADLPWriteResGroup231], (instrs SHA256MSG2rr)>;
-def ADLPWriteResGroup231 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup232 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
let Latency = 13;
let NumMicroOps = 5;
}
-def : InstRW<[ADLPWriteResGroup231], (instregex "^SHRD16mri8$")>;
+def : InstRW<[ADLPWriteResGroup232], (instrs SHRD16mri8)>;
-def ADLPWriteResGroup232 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort01]> {
+def ADLPWriteResGroup233 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort01]> {
let Latency = 6;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup232], (instregex "^SLDT(32|64)r$")>;
+def : InstRW<[ADLPWriteResGroup233], (instregex "^SLDT(32|64)r$")>;
-def ADLPWriteResGroup233 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort05]> {
+def ADLPWriteResGroup234 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort05]> {
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup233], (instregex "^SMSW16r$")>;
+def : InstRW<[ADLPWriteResGroup234], (instrs SMSW16r)>;
-def ADLPWriteResGroup234 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort05]> {
+def ADLPWriteResGroup235 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort05]> {
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup234], (instregex "^SMSW(32|64)r$")>;
+def : InstRW<[ADLPWriteResGroup235], (instregex "^SMSW(32|64)r$")>;
-def ADLPWriteResGroup235 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06]> {
+def ADLPWriteResGroup236 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06]> {
let Latency = 6;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup235], (instregex "^STD$")>;
+def : InstRW<[ADLPWriteResGroup236], (instrs STD)>;
-def ADLPWriteResGroup236 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
+def ADLPWriteResGroup237 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
let ResourceCycles = [1, 4, 1];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 6;
}
-def : InstRW<[ADLPWriteResGroup236], (instregex "^STI$")>;
+def : InstRW<[ADLPWriteResGroup237], (instrs STI)>;
-def ADLPWriteResGroup237 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup238 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort04_09, ADLPPort07_08]> {
let ResourceCycles = [2, 1, 1];
let Latency = 8;
let NumMicroOps = 4;
}
-def : InstRW<[ADLPWriteResGroup237], (instregex "^STOSB$")>;
+def : InstRW<[ADLPWriteResGroup238], (instrs STOSB)>;
-def ADLPWriteResGroup238 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup239 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort04_09, ADLPPort07_08]> {
let ResourceCycles = [2, 1, 1];
let Latency = 7;
let NumMicroOps = 4;
}
-def : InstRW<[ADLPWriteResGroup238], (instregex "^STOS(L|Q|W)$")>;
+def : InstRW<[ADLPWriteResGroup239], (instregex "^STOS(L|Q|W)$")>;
-def ADLPWriteResGroup239 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort01]> {
+def ADLPWriteResGroup240 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort01]> {
let Latency = 5;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup239], (instregex "^STR(32|64)r$")>;
+def : InstRW<[ADLPWriteResGroup240], (instregex "^STR(32|64)r$")>;
-def ADLPWriteResGroup240 : SchedWriteRes<[ADLPPort00]> {
+def ADLPWriteResGroup241 : SchedWriteRes<[ADLPPort00]> {
let Latency = 2;
}
-def : InstRW<[ADLPWriteResGroup240], (instregex "^(TST|XAM)_F$",
- "^UCOM_FPPr$")>;
+def : InstRW<[ADLPWriteResGroup241], (instregex "^(TST|XAM)_F$")>;
+def : InstRW<[ADLPWriteResGroup241], (instrs UCOM_FPPr)>;
-def ADLPWriteResGroup241 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort02_03_11]> {
+def ADLPWriteResGroup242 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort02_03_11]> {
let ResourceCycles = [3, 1];
let Latency = 9;
let NumMicroOps = 4;
}
-def : InstRW<[ADLPWriteResGroup241, ReadAfterVecXLd, ReadAfterVecXLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^VBLENDVP(D|S)rm$",
- "^VPBLENDVBrm$")>;
+def : InstRW<[ADLPWriteResGroup242, ReadAfterVecXLd, ReadAfterVecXLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^VBLENDVP(D|S)rm$")>;
+def : InstRW<[ADLPWriteResGroup242, ReadAfterVecXLd, ReadAfterVecXLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instrs VPBLENDVBrm)>;
-def ADLPWriteResGroup242 : SchedWriteRes<[ADLPPort00_01_05]> {
+def ADLPWriteResGroup243 : SchedWriteRes<[ADLPPort00_01_05]> {
let ResourceCycles = [3];
let Latency = 3;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup242], (instregex "^VBLENDVP(D|S)rr$",
- "^VPBLENDVBrr$")>;
+def : InstRW<[ADLPWriteResGroup243], (instregex "^VBLENDVP(D|S)rr$")>;
+def : InstRW<[ADLPWriteResGroup243], (instrs VPBLENDVBrr)>;
-def ADLPWriteResGroup243 : SchedWriteRes<[ADLPPort00, ADLPPort01, ADLPPort02_03_11]> {
+def ADLPWriteResGroup244 : SchedWriteRes<[ADLPPort00, ADLPPort01, ADLPPort02_03_11]> {
let ResourceCycles = [6, 7, 18];
let Latency = 81;
let NumMicroOps = 31;
}
-def : InstRW<[ADLPWriteResGroup243], (instregex "^VERRm$")>;
+def : InstRW<[ADLPWriteResGroup244], (instrs VERRm)>;
-def ADLPWriteResGroup244 : SchedWriteRes<[ADLPPort00, ADLPPort01, ADLPPort02_03_11]> {
+def ADLPWriteResGroup245 : SchedWriteRes<[ADLPPort00, ADLPPort01, ADLPPort02_03_11]> {
let ResourceCycles = [6, 7, 17];
let Latency = 74;
let NumMicroOps = 30;
}
-def : InstRW<[ADLPWriteResGroup244], (instregex "^VERRr$")>;
+def : InstRW<[ADLPWriteResGroup245], (instrs VERRr)>;
-def ADLPWriteResGroup245 : SchedWriteRes<[ADLPPort00, ADLPPort01, ADLPPort02_03_11]> {
+def ADLPWriteResGroup246 : SchedWriteRes<[ADLPPort00, ADLPPort01, ADLPPort02_03_11]> {
let ResourceCycles = [5, 8, 21];
let Latency = 81;
let NumMicroOps = 34;
}
-def : InstRW<[ADLPWriteResGroup245], (instregex "^VERWm$")>;
+def : InstRW<[ADLPWriteResGroup246], (instrs VERWm)>;
-def ADLPWriteResGroup246 : SchedWriteRes<[ADLPPort00, ADLPPort01, ADLPPort02_03_11]> {
+def ADLPWriteResGroup247 : SchedWriteRes<[ADLPPort00, ADLPPort01, ADLPPort02_03_11]> {
let ResourceCycles = [5, 8, 20];
let Latency = 74;
let NumMicroOps = 33;
}
-def : InstRW<[ADLPWriteResGroup246], (instregex "^VERWr$")>;
+def : InstRW<[ADLPWriteResGroup247], (instrs VERWr)>;
-def ADLPWriteResGroup247 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort01_05, ADLPPort02_03_11]> {
+def ADLPWriteResGroup248 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort01_05, ADLPPort02_03_11]> {
let ResourceCycles = [1, 1, 2, 4];
let Latency = 29;
let NumMicroOps = 8;
}
-def : InstRW<[ADLPWriteResGroup247, WriteVecMaskedGatherWriteback], (instregex "^VGATHER(DPD|QPS)Yrm$",
- "^VGATHERQPDYrm$",
- "^VPGATHER(D|Q)QYrm$",
- "^VPGATHERQDYrm$")>;
+def : InstRW<[ADLPWriteResGroup248, WriteVecMaskedGatherWriteback], (instregex "^VGATHER(DPD|QPS)Yrm$",
+ "^VPGATHER(D|Q)QYrm$")>;
+def : InstRW<[ADLPWriteResGroup248, WriteVecMaskedGatherWriteback], (instrs VGATHERQPDYrm,
+ VPGATHERQDYrm)>;
-def ADLPWriteResGroup248 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort01_05, ADLPPort02_03_11]> {
+def ADLPWriteResGroup249 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort01_05, ADLPPort02_03_11]> {
let ResourceCycles = [1, 1, 1, 2];
let Latency = 20;
let NumMicroOps = 5;
}
-def : InstRW<[ADLPWriteResGroup248, WriteVecMaskedGatherWriteback], (instregex "^VGATHER(DPD|QPS)rm$",
- "^VGATHERQPDrm$",
- "^VPGATHER(D|Q)Qrm$",
- "^VPGATHERQDrm$")>;
+def : InstRW<[ADLPWriteResGroup249, WriteVecMaskedGatherWriteback], (instregex "^VGATHER(DPD|QPS)rm$",
+ "^VPGATHER(D|Q)Qrm$")>;
+def : InstRW<[ADLPWriteResGroup249, WriteVecMaskedGatherWriteback], (instrs VGATHERQPDrm,
+ VPGATHERQDrm)>;
-def ADLPWriteResGroup249 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort01_05, ADLPPort02_03_11]> {
+def ADLPWriteResGroup250 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort01_05, ADLPPort02_03_11]> {
let ResourceCycles = [1, 1, 2, 8];
let Latency = 30;
let NumMicroOps = 12;
}
-def : InstRW<[ADLPWriteResGroup249, WriteVecMaskedGatherWriteback], (instregex "^VGATHERDPSYrm$",
- "^VPGATHERDDYrm$")>;
+def : InstRW<[ADLPWriteResGroup250, WriteVecMaskedGatherWriteback], (instrs VGATHERDPSYrm,
+ VPGATHERDDYrm)>;
-def ADLPWriteResGroup250 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort01_05, ADLPPort02_03_11]> {
+def ADLPWriteResGroup251 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort01_05, ADLPPort02_03_11]> {
let ResourceCycles = [1, 1, 2, 4];
let Latency = 28;
let NumMicroOps = 8;
}
-def : InstRW<[ADLPWriteResGroup250, WriteVecMaskedGatherWriteback], (instregex "^VGATHERDPSrm$",
- "^VPGATHERDDrm$")>;
+def : InstRW<[ADLPWriteResGroup251, WriteVecMaskedGatherWriteback], (instrs VGATHERDPSrm,
+ VPGATHERDDrm)>;
-def ADLPWriteResGroup251 : SchedWriteRes<[ADLPPort01_05, ADLPPort05]> {
+def ADLPWriteResGroup252 : SchedWriteRes<[ADLPPort01_05, ADLPPort05]> {
let ResourceCycles = [1, 2];
let Latency = 5;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup251], (instregex "^VH(ADD|SUB)P(D|S)rr$")>;
+def : InstRW<[ADLPWriteResGroup252], (instregex "^VH(ADD|SUB)P(D|S)rr$")>;
-def ADLPWriteResGroup252 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort02_03_11]> {
+def ADLPWriteResGroup253 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort02_03_11]> {
let Latency = 9;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup252, ReadAfterVecYLd], (instregex "^VINSERT(F|I)128rm$",
+def : InstRW<[ADLPWriteResGroup253, ReadAfterVecYLd], (instregex "^VINSERT(F|I)128rm$",
"^VP(ADD|SUB)(B|D|Q|W)Yrm$")>;
-def ADLPWriteResGroup253 : SchedWriteRes<[ADLPPort00, ADLPPort00_06, ADLPPort02_03_11]> {
+def ADLPWriteResGroup254 : SchedWriteRes<[ADLPPort00, ADLPPort00_06, ADLPPort02_03_11]> {
let Latency = 7;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup253], (instregex "^VLDMXCSR$")>;
+def : InstRW<[ADLPWriteResGroup254], (instrs VLDMXCSR)>;
-def ADLPWriteResGroup254 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03, ADLPPort02_03_07, ADLPPort04, ADLPPort05, ADLPPort06]> {
+def ADLPWriteResGroup255 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03, ADLPPort02_03_07, ADLPPort04, ADLPPort05, ADLPPort06]> {
let ResourceCycles = [8, 1, 1, 1, 1, 1, 2, 3];
let Latency = 40;
let NumMicroOps = 18;
}
-def : InstRW<[ADLPWriteResGroup254], (instregex "^VMCLEARm$")>;
+def : InstRW<[ADLPWriteResGroup255], (instrs VMCLEARm)>;
-def ADLPWriteResGroup255 : SchedWriteRes<[ADLPPort00]> {
+def ADLPWriteResGroup256 : SchedWriteRes<[ADLPPort00]> {
let Latency = 5;
}
-def : InstRW<[ADLPWriteResGroup255], (instregex "^VMOVMSKP(D|S)Yrr$")>;
+def : InstRW<[ADLPWriteResGroup256], (instregex "^VMOVMSKP(D|S)Yrr$")>;
-def ADLPWriteResGroup256 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup257 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
let Latency = 521;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup256], (instregex "^VMOVNTDQmr$")>;
+def : InstRW<[ADLPWriteResGroup257], (instrs VMOVNTDQmr)>;
-def ADLPWriteResGroup257 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup258 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
let Latency = 473;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup257], (instregex "^VMOVNTPDmr$")>;
+def : InstRW<[ADLPWriteResGroup258], (instrs VMOVNTPDmr)>;
-def ADLPWriteResGroup258 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup259 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
let Latency = 494;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup258], (instregex "^VMOVNTPSYmr$")>;
+def : InstRW<[ADLPWriteResGroup259], (instrs VMOVNTPSYmr)>;
-def ADLPWriteResGroup259 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup260 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
let Latency = 470;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup259], (instregex "^VMOVNTPSmr$")>;
+def : InstRW<[ADLPWriteResGroup260], (instrs VMOVNTPSmr)>;
-def ADLPWriteResGroup260 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup261 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
let Latency = 11;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup260, ReadAfterVecYLd], (instregex "^VPACK(S|U)S(DW|WB)Yrm$",
- "^VPCMPGTQYrm$")>;
-def : InstRW<[ADLPWriteResGroup260, ReadAfterVecXLd], (instregex "^VPCLMULQDQYrm$")>;
+def : InstRW<[ADLPWriteResGroup261, ReadAfterVecYLd], (instregex "^VPACK(S|U)S(DW|WB)Yrm$")>;
+def : InstRW<[ADLPWriteResGroup261, ReadAfterVecYLd], (instrs VPCMPGTQYrm)>;
+def : InstRW<[ADLPWriteResGroup261, ReadAfterVecXLd], (instrs VPCLMULQDQYrm)>;
-def ADLPWriteResGroup261 : SchedWriteRes<[ADLPPort01_05, ADLPPort02_03_11]> {
+def ADLPWriteResGroup262 : SchedWriteRes<[ADLPPort01_05, ADLPPort02_03_11]> {
let Latency = 9;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup261, ReadAfterVecYLd], (instregex "^VPBLENDWYrmi$",
- "^VSHUFP(D|S)Yrmi$")>;
+def : InstRW<[ADLPWriteResGroup262, ReadAfterVecYLd], (instregex "^VSHUFP(D|S)Yrmi$")>;
+def : InstRW<[ADLPWriteResGroup262, ReadAfterVecYLd], (instrs VPBLENDWYrmi)>;
-def ADLPWriteResGroup262 : SchedWriteRes<[ADLPPort00_01, ADLPPort02_03_11]> {
+def ADLPWriteResGroup263 : SchedWriteRes<[ADLPPort00_01, ADLPPort02_03_11]> {
let Latency = 13;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup262], (instregex "^VPDP(BU|WS)SD((SY)?)rm$",
+def : InstRW<[ADLPWriteResGroup263], (instregex "^VPDP(BU|WS)SD((SY)?)rm$",
"^VPDP(BU|WS)SD(S|Y)rm$")>;
-def ADLPWriteResGroup263 : SchedWriteRes<[ADLPPort00_01, ADLPPort01_05, ADLPPort02_03_11]> {
+def ADLPWriteResGroup264 : SchedWriteRes<[ADLPPort00_01, ADLPPort01_05, ADLPPort02_03_11]> {
let ResourceCycles = [1, 2, 1];
let Latency = 10;
let NumMicroOps = 4;
}
-def : InstRW<[ADLPWriteResGroup263, ReadAfterVecYLd], (instregex "^VPH(ADD|SUB)SWYrm$")>;
+def : InstRW<[ADLPWriteResGroup264, ReadAfterVecYLd], (instregex "^VPH(ADD|SUB)SWYrm$")>;
-def ADLPWriteResGroup264 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10]> {
+def ADLPWriteResGroup265 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10]> {
let ResourceCycles = [1, 2, 3, 3, 1];
let Latency = 16;
let NumMicroOps = 10;
}
-def : InstRW<[ADLPWriteResGroup264], (instregex "^VZEROALL$")>;
+def : InstRW<[ADLPWriteResGroup265], (instrs VZEROALL)>;
-def ADLPWriteResGroup265 : SchedWriteRes<[ADLPPort00_01_05_06]> {
+def ADLPWriteResGroup266 : SchedWriteRes<[ADLPPort00_01_05_06]> {
let ResourceCycles = [2];
let Latency = 2;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup265], (instregex "^WAIT$")>;
+def : InstRW<[ADLPWriteResGroup266], (instrs WAIT)>;
-def ADLPWriteResGroup266 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup267 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [8, 6, 19, 63, 21, 15, 1, 10, 1];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 144;
}
-def : InstRW<[ADLPWriteResGroup266], (instregex "^WRMSR$")>;
+def : InstRW<[ADLPWriteResGroup267], (instrs WRMSR)>;
-def ADLPWriteResGroup267 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort05]> {
+def ADLPWriteResGroup268 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort05]> {
let ResourceCycles = [2, 1, 4, 1];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 8;
}
-def : InstRW<[ADLPWriteResGroup267], (instregex "^WRPKRUr$")>;
+def : InstRW<[ADLPWriteResGroup268], (instrs WRPKRUr)>;
-def ADLPWriteResGroup268 : SchedWriteRes<[ADLPPort00_01_05_06_10]> {
+def ADLPWriteResGroup269 : SchedWriteRes<[ADLPPort00_01_05_06_10]> {
let ResourceCycles = [2];
let Latency = 12;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup268, WriteRMW], (instregex "^XADD(16|32|64)rm$")>;
+def : InstRW<[ADLPWriteResGroup269, WriteRMW], (instregex "^XADD(16|32|64)rm$")>;
-def ADLPWriteResGroup269 : SchedWriteRes<[ADLPPort00_01_05_06_10]> {
+def ADLPWriteResGroup270 : SchedWriteRes<[ADLPPort00_01_05_06_10]> {
let ResourceCycles = [2];
let Latency = 13;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup269, WriteRMW], (instregex "^XADD8rm$")>;
+def : InstRW<[ADLPWriteResGroup270, WriteRMW], (instrs XADD8rm)>;
-def ADLPWriteResGroup270 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06]> {
+def ADLPWriteResGroup271 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06]> {
let ResourceCycles = [4, 1];
let Latency = 39;
let NumMicroOps = 5;
}
-def : InstRW<[ADLPWriteResGroup270, WriteRMW], (instregex "^XCHG(16|32)rm$")>;
+def : InstRW<[ADLPWriteResGroup271, WriteRMW], (instregex "^XCHG(16|32)rm$")>;
-def ADLPWriteResGroup271 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06]> {
+def ADLPWriteResGroup272 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06]> {
let ResourceCycles = [5, 1];
let Latency = 39;
let NumMicroOps = 6;
}
-def : InstRW<[ADLPWriteResGroup271, WriteRMW], (instregex "^XCHG64rm$")>;
+def : InstRW<[ADLPWriteResGroup272, WriteRMW], (instrs XCHG64rm)>;
-def ADLPWriteResGroup272 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06]> {
+def ADLPWriteResGroup273 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06]> {
let ResourceCycles = [4, 1];
let Latency = 40;
let NumMicroOps = 5;
}
-def : InstRW<[ADLPWriteResGroup272, WriteRMW], (instregex "^XCHG8rm$")>;
+def : InstRW<[ADLPWriteResGroup273, WriteRMW], (instrs XCHG8rm)>;
-def ADLPWriteResGroup273 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06, ADLPPort00_05, ADLPPort01, ADLPPort05, ADLPPort06]> {
+def ADLPWriteResGroup274 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06, ADLPPort00_05, ADLPPort01, ADLPPort05, ADLPPort06]> {
let ResourceCycles = [2, 4, 2, 1, 2, 4];
let Latency = 17;
let NumMicroOps = 15;
}
-def : InstRW<[ADLPWriteResGroup273], (instregex "^XCH_F$")>;
+def : InstRW<[ADLPWriteResGroup274], (instrs XCH_F)>;
-def ADLPWriteResGroup274 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01]> {
+def ADLPWriteResGroup275 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01]> {
let ResourceCycles = [7, 3, 8, 5];
let Latency = 4;
let NumMicroOps = 23;
}
-def : InstRW<[ADLPWriteResGroup274], (instregex "^XGETBV$")>;
+def : InstRW<[ADLPWriteResGroup275], (instrs XGETBV)>;
-def ADLPWriteResGroup275 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
+def ADLPWriteResGroup276 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
let ResourceCycles = [2, 1];
let Latency = 7;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup275], (instregex "^XLAT$")>;
+def : InstRW<[ADLPWriteResGroup276], (instrs XLAT)>;
-def ADLPWriteResGroup276 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort01, ADLPPort02_03, ADLPPort06]> {
+def ADLPWriteResGroup277 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort01, ADLPPort02_03, ADLPPort06]> {
let ResourceCycles = [21, 1, 1, 8];
let Latency = 37;
let NumMicroOps = 31;
}
-def : InstRW<[ADLPWriteResGroup276], (instregex "^XRSTOR((S|64|S64)?)$")>;
+def : InstRW<[ADLPWriteResGroup277], (instregex "^XRSTOR((S|64|S64)?)$")>;
-def ADLPWriteResGroup277 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup278 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [14, 25, 44, 21, 21, 4, 1, 9, 1];
let Latency = 42;
let NumMicroOps = 140;
}
-def : InstRW<[ADLPWriteResGroup277], (instregex "^XSAVE$")>;
+def : InstRW<[ADLPWriteResGroup278], (instrs XSAVE)>;
-def ADLPWriteResGroup278 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup279 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [14, 25, 44, 21, 21, 4, 1, 9, 1];
let Latency = 41;
let NumMicroOps = 140;
}
-def : InstRW<[ADLPWriteResGroup278], (instregex "^XSAVE64$")>;
+def : InstRW<[ADLPWriteResGroup279], (instrs XSAVE64)>;
-def ADLPWriteResGroup279 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup280 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [1, 19, 36, 52, 23, 4, 2, 12, 2];
let Latency = 42;
let NumMicroOps = 151;
}
-def : InstRW<[ADLPWriteResGroup279], (instregex "^XSAVEC$")>;
+def : InstRW<[ADLPWriteResGroup280], (instrs XSAVEC)>;
-def ADLPWriteResGroup280 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup281 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [1, 19, 36, 53, 23, 4, 2, 12, 2];
let Latency = 42;
let NumMicroOps = 152;
}
-def : InstRW<[ADLPWriteResGroup280], (instregex "^XSAVEC64$")>;
+def : InstRW<[ADLPWriteResGroup281], (instrs XSAVEC64)>;
-def ADLPWriteResGroup281 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup282 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [25, 35, 52, 27, 4, 1, 10, 1];
let Latency = 46;
let NumMicroOps = 155;
}
-def : InstRW<[ADLPWriteResGroup281], (instregex "^XSAVEOPT$")>;
+def : InstRW<[ADLPWriteResGroup282], (instrs XSAVEOPT)>;
-def ADLPWriteResGroup282 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup283 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [25, 35, 53, 27, 4, 1, 10, 1];
let Latency = 46;
let NumMicroOps = 156;
}
-def : InstRW<[ADLPWriteResGroup282], (instregex "^XSAVEOPT64$")>;
+def : InstRW<[ADLPWriteResGroup283], (instrs XSAVEOPT64)>;
-def ADLPWriteResGroup283 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup284 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [23, 32, 53, 29, 30, 4, 2, 9, 2];
let Latency = 42;
let NumMicroOps = 184;
}
-def : InstRW<[ADLPWriteResGroup283], (instregex "^XSAVES$")>;
+def : InstRW<[ADLPWriteResGroup284], (instrs XSAVES)>;
-def ADLPWriteResGroup284 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup285 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [23, 33, 53, 29, 32, 4, 2, 8, 2];
let Latency = 42;
let NumMicroOps = 186;
}
-def : InstRW<[ADLPWriteResGroup284], (instregex "^XSAVES64$")>;
+def : InstRW<[ADLPWriteResGroup285], (instrs XSAVES64)>;
-def ADLPWriteResGroup285 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort05]> {
+def ADLPWriteResGroup286 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort05]> {
let ResourceCycles = [4, 23, 2, 14, 8, 1, 2];
let Latency = 5;
let NumMicroOps = 54;
}
-def : InstRW<[ADLPWriteResGroup285], (instregex "^XSETBV$")>;
+def : InstRW<[ADLPWriteResGroup286], (instrs XSETBV)>;
}
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