[llvm] 2179f51 - [AArch64][GlobalISel] Select TBZ for icmp sge x, 0.

[Amara Emerson via llvm-commits]

Author: Amara Emerson
Date: 2022-11-11T20:15:46-08:00
New Revision: 2179f513356116aa30e2ecffb461f9de94f65475

URL: https://github.com/llvm/llvm-project/commit/2179f513356116aa30e2ecffb461f9de94f65475
DIFF: https://github.com/llvm/llvm-project/commit/2179f513356116aa30e2ecffb461f9de94f65475.diff

LOG: [AArch64][GlobalISel] Select TBZ for icmp sge x, 0.

This results in some nice size improvements on -Os CTMark:
Program                                       size.__text
                                              sdag           gisel           diff
consumer-typeset/consumer-typeset             414124.00      414052.00      -0.0%
tramp3d-v4/tramp3d-v4                         356840.00      356732.00      -0.0%
lencod/lencod                                 427560.00      427396.00      -0.0%
7zip/7zip-benchmark                           568400.00      568172.00      -0.0%
Bullet/bullet                                 455660.00      455428.00      -0.1%
mafft/pairlocalalign                          248236.00      248040.00      -0.1%
sqlite3/sqlite3                               284404.00      284176.00      -0.1%
ClamAV/clamscan                               381052.00      380604.00      -0.1%
SPASS/SPASS                                   411932.00      411296.00      -0.2%
kimwitu++/kc                                  439696.00      438992.00      -0.2%
                           Geomean difference                               -0.1%

Added: 
    llvm/test/CodeGen/AArch64/GlobalISel/select-tbnz-from-cmp.mir

Modified: 
    llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

Removed: 
    llvm/test/CodeGen/AArch64/GlobalISel/tbnz-slt.mir


################################################################################
diff  --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index bc9277f861be6..f14f7c4bb45db 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -1682,6 +1682,15 @@ bool AArch64InstructionSelector::tryOptCompareBranchFedByICmp(
       I.eraseFromParent();
       return true;
     }
+
+    // Inversely, if we have a signed greater-than-or-equal comparison to zero,
+    // we can test if the msb is zero.
+    if (C == 0 && Pred == CmpInst::ICMP_SGE) {
+      uint64_t Bit = MRI.getType(LHS).getSizeInBits() - 1;
+      emitTestBit(LHS, Bit, /*IsNegative = */ false, DestMBB, MIB);
+      I.eraseFromParent();
+      return true;
+    }
   }
 
   // Attempt to handle commutative condition codes. Right now, that's only

diff  --git a/llvm/test/CodeGen/AArch64/GlobalISel/tbnz-slt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-tbnz-from-cmp.mir
similarity index 75%
rename from llvm/test/CodeGen/AArch64/GlobalISel/tbnz-slt.mir
rename to llvm/test/CodeGen/AArch64/GlobalISel/select-tbnz-from-cmp.mir
index ce87e73b6d0f2..30db00aa97813 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/tbnz-slt.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-tbnz-from-cmp.mir
@@ -64,6 +64,64 @@ body:             |
   bb.1:
     RET_ReallyLR
 
+...
+---
+name:            tbnzx_sge
+alignment:       4
+legalized:       true
+regBankSelected: true
+body:             |
+  ; CHECK-LABEL: name: tbnzx_sge
+  ; CHECK: bb.0:
+  ; CHECK-NEXT:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
+  ; CHECK-NEXT:   liveins: $x0
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   %copy:gpr64 = COPY $x0
+  ; CHECK-NEXT:   TBZX %copy, 63, %bb.1
+  ; CHECK-NEXT:   B %bb.0
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1:
+  ; CHECK-NEXT:   RET_ReallyLR
+  bb.0:
+    successors: %bb.0, %bb.1
+    liveins: $x0
+    %copy:gpr(s64) = COPY $x0
+    %zero:gpr(s64) = G_CONSTANT i64 0
+    %cmp:gpr(s32) = G_ICMP intpred(sge), %copy(s64), %zero
+    G_BRCOND %cmp, %bb.1
+    G_BR %bb.0
+  bb.1:
+    RET_ReallyLR
+
+...
+---
+name:            tbnzw_sge
+alignment:       4
+legalized:       true
+regBankSelected: true
+body:             |
+  ; CHECK-LABEL: name: tbnzw_sge
+  ; CHECK: bb.0:
+  ; CHECK-NEXT:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
+  ; CHECK-NEXT:   liveins: $x0
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   %copy:gpr32 = COPY $w0
+  ; CHECK-NEXT:   TBZW %copy, 31, %bb.1
+  ; CHECK-NEXT:   B %bb.0
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1:
+  ; CHECK-NEXT:   RET_ReallyLR
+  bb.0:
+    successors: %bb.0, %bb.1
+    liveins: $x0
+    %copy:gpr(s32) = COPY $w0
+    %zero:gpr(s32) = G_CONSTANT i32 0
+    %cmp:gpr(s32) = G_ICMP intpred(sge), %copy(s32), %zero
+    G_BRCOND %cmp, %bb.1
+    G_BR %bb.0
+  bb.1:
+    RET_ReallyLR
+
 ...
 ---
 name:            no_tbnz_not_zero