[PATCH] D137699: [RISCV] Don't use zero-stride vector load if there's no optimized u-arch

[Wang Pengcheng via Phabricator via llvm-commits]

pcwang-thead added a comment.

In D137699#3919799 <https://reviews.llvm.org/D137699#3919799>, @reames wrote:

> I have no problem with adding a feature to disable this optimization, but there's two problems with this patch.
>
> First, a bunch of existing CPUs do support this optimization.  Your change doesn't update any of them, so this is strictly a regression.
>
> Second, most designs I'm aware of do implement this optimization.  As such, I really think this patch gets the default wrong.  We should allow disabling optimizations for code targeting designs which don't optimize this case, but if we're targeting a generic riscv64 vector core, assuming this optimization should be the default.

Thanks! I do agree with you and I have made it default now.

> Also, are you are of a specific design which doesn't optimize this case?  If not, the complexity doesn't seem worthwhile.

Yes, some of our taped-out low-end products didn't do this optimization.


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