[llvm] 0436cf5 - [LoongArch] Support parsing target specific flags for MIR

[via llvm-commits]

Author: wanglei
Date: 2022-11-10T20:53:20+08:00
New Revision: 0436cf5f52175a2a97d4cf2ff30fac54df7645b5

URL: https://github.com/llvm/llvm-project/commit/0436cf5f52175a2a97d4cf2ff30fac54df7645b5
DIFF: https://github.com/llvm/llvm-project/commit/0436cf5f52175a2a97d4cf2ff30fac54df7645b5.diff

LOG: [LoongArch] Support parsing target specific flags for MIR

These hooks ensure that the LoongArch backend can serialize and parse
MIR correctly.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D137482

Added: 
    llvm/test/CodeGen/LoongArch/mir-target-flags.ll

Modified: 
    llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp
    llvm/lib/Target/LoongArch/LoongArchInstrInfo.h

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp
index 00b806a8909d..eab5cdb61aef 100644
--- a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp
@@ -434,3 +434,28 @@ bool LoongArchInstrInfo::reverseBranchCondition(
   Cond[0].setImm(getOppositeBranchOpc(Cond[0].getImm()));
   return false;
 }
+
+std::pair<unsigned, unsigned>
+LoongArchInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
+  return std::make_pair(TF, 0u);
+}
+
+ArrayRef<std::pair<unsigned, const char *>>
+LoongArchInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
+  using namespace LoongArchII;
+  // TODO: Add more target flags.
+  static const std::pair<unsigned, const char *> TargetFlags[] = {
+      {MO_CALL, "loongarch-call"},
+      {MO_CALL_PLT, "loongarch-call-plt"},
+      {MO_PCREL_HI, "loongarch-pcrel-hi"},
+      {MO_PCREL_LO, "loongarch-pcrel-lo"},
+      {MO_GOT_PC_HI, "loongarch-got-pc-hi"},
+      {MO_GOT_PC_LO, "loongarch-got-pc-lo"},
+      {MO_LE_HI, "loongarch-le-hi"},
+      {MO_LE_LO, "loongarch-le-lo"},
+      {MO_IE_PC_HI, "loongarch-ie-pc-hi"},
+      {MO_IE_PC_LO, "loongarch-ie-pc-lo"},
+      {MO_LD_PC_HI, "loongarch-ld-pc-hi"},
+      {MO_GD_PC_HI, "loongarch-gd-pc-hi"}};
+  return makeArrayRef(TargetFlags);
+}

diff  --git a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.h b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.h
index 633d3eba50c0..71bc330f7879 100644
--- a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.h
+++ b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.h
@@ -74,6 +74,12 @@ class LoongArchInstrInfo : public LoongArchGenInstrInfo {
   bool
   reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
 
+  std::pair<unsigned, unsigned>
+  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
+
+  ArrayRef<std::pair<unsigned, const char *>>
+  getSerializableDirectMachineOperandTargetFlags() const override;
+
 protected:
   const LoongArchSubtarget &STI;
 };

diff  --git a/llvm/test/CodeGen/LoongArch/mir-target-flags.ll b/llvm/test/CodeGen/LoongArch/mir-target-flags.ll
new file mode 100644
index 000000000000..9f3a061fe724
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/mir-target-flags.ll
@@ -0,0 +1,44 @@
+; RUN: llc --mtriple=loongarch64 --stop-after loongarch-prera-expand-pseudo \
+; RUN:     --relocation-model=pic %s -o %t.mir
+; RUN: llc --mtriple=loongarch64 --run-pass loongarch-prera-expand-pseudo \
+; RUN:     %t.mir -o - | FileCheck %s
+
+;; This tests the LoongArch-specific serialization and deserialization of
+;; `target-flags(...)`
+
+ at g_e = external global i32
+ at g_i = internal global i32 0
+ at t_un = external thread_local global i32
+ at t_ld = external thread_local(localdynamic) global i32
+ at t_ie = external thread_local(initialexec) global i32
+ at t_le = external thread_local(localexec) global i32
+
+declare void @callee1() nounwind
+declare dso_local void @callee2() nounwind
+
+define void @caller() nounwind {
+; CHECK-LABEL: name: caller
+; CHECK:      target-flags(loongarch-got-pc-hi) @g_e
+; CHECK-NEXT: target-flags(loongarch-got-pc-lo) @g_e
+; CHECK:      target-flags(loongarch-pcrel-hi) @g_i
+; CHECK-NEXT: target-flags(loongarch-pcrel-lo) @g_i
+; CHECK:      target-flags(loongarch-gd-pc-hi) @t_un
+; CHECK-NEXT: target-flags(loongarch-got-pc-lo) @t_un
+; CHECK:      target-flags(loongarch-ld-pc-hi) @t_ld
+; CHECK-NEXT: target-flags(loongarch-got-pc-lo) @t_ld
+; CHECK:      target-flags(loongarch-ie-pc-hi) @t_ie
+; CHECK-NEXT: target-flags(loongarch-ie-pc-lo) @t_ie
+; CHECK:      target-flags(loongarch-le-hi) @t_le
+; CHECK-NEXT: target-flags(loongarch-le-lo) @t_le
+; CHECK:      target-flags(loongarch-call-plt) @callee1
+; CHECK:      target-flags(loongarch-call) @callee2
+  %a = load volatile i32, ptr @g_e
+  %b = load volatile i32, ptr @g_i
+  %c = load volatile i32, ptr @t_un
+  %d = load volatile i32, ptr @t_ld
+  %e = load volatile i32, ptr @t_ie
+  %f = load volatile i32, ptr @t_le
+  call i32 @callee1()
+  call i32 @callee2()
+  ret void
+}