[llvm] 926acd2 - [AMDGPU][AsmParser] Remove extra checks on missing instruction modifiers.

[Ivan Kosarev via llvm-commits]

Author: Ivan Kosarev
Date: 2022-11-10T12:49:27Z
New Revision: 926acd2bb55d8deed96b134a12321ee6725671f4

URL: https://github.com/llvm/llvm-project/commit/926acd2bb55d8deed96b134a12321ee6725671f4
DIFF: https://github.com/llvm/llvm-project/commit/926acd2bb55d8deed96b134a12321ee6725671f4.diff

LOG: [AMDGPU][AsmParser] Remove extra checks on missing instruction modifiers.

https://reviews.llvm.org/D137549 makes them unnecessary.

Reviewed By: dp

Differential Revision: https://reviews.llvm.org/D137638

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index c1eb61f2f4ac2..4fb9f137a8086 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -1673,7 +1673,6 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
   bool validateMIMGDataSize(const MCInst &Inst, const SMLoc &IDLoc);
   bool validateMIMGAddrSize(const MCInst &Inst);
   bool validateMIMGD16(const MCInst &Inst);
-  bool validateMIMGDim(const MCInst &Inst);
   bool validateMIMGMSAA(const MCInst &Inst);
   bool validateOpSel(const MCInst &Inst);
   bool validateDPP(const MCInst &Inst, const OperandVector &Operands);
@@ -1690,8 +1689,6 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
   bool validateWaitCnt(const MCInst &Inst, const OperandVector &Operands);
   bool validateCoherencyBits(const MCInst &Inst, const OperandVector &Operands,
                              const SMLoc &IDLoc);
-  bool validateLdsDMA(uint64_t Enc, const MCInst &Inst,
-                      const OperandVector &Operands, const SMLoc &IDLoc);
   bool validateExeczVcczOperands(const OperandVector &Operands);
   Optional<StringRef> validateLdsDirect(const MCInst &Inst);
   unsigned getConstantBusLimit(unsigned Opcode) const;
@@ -3956,24 +3953,6 @@ bool AMDGPUAsmParser::validateMIMGD16(const MCInst &Inst) {
   return true;
 }
 
-bool AMDGPUAsmParser::validateMIMGDim(const MCInst &Inst) {
-  const unsigned Opc = Inst.getOpcode();
-  const MCInstrDesc &Desc = MII.get(Opc);
-
-  if ((Desc.TSFlags & SIInstrFlags::MIMG) == 0)
-    return true;
-
-  int DimIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dim);
-  if (DimIdx < 0)
-    return true;
-
-  int64_t Imm = Inst.getOperand(DimIdx).getImm();
-  if (Imm < 0 || Imm >= 8)
-    return false;
-
-  return true;
-}
-
 static bool IsRevOpcode(const unsigned Opcode)
 {
   switch (Opcode) {
@@ -4601,37 +4580,6 @@ bool AMDGPUAsmParser::validateCoherencyBits(const MCInst &Inst,
   return true;
 }
 
-bool AMDGPUAsmParser::validateLdsDMA(uint64_t Enc, const MCInst &Inst,
-                                     const OperandVector &Operands,
-                                     const SMLoc &IDLoc) {
-  assert(Enc == SIInstrFlags::FLAT || Enc == SIInstrFlags::MUBUF);
-
-  // Exclude cases when there are separate DMA opcodes.
-  // In these cases, incorrect opcode selection is not possible.
-  if (Enc == SIInstrFlags::FLAT && isGFX940())
-    return true;
-  if (Enc == SIInstrFlags::MUBUF && isGFX11Plus())
-    return true;
-
-  uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags;
-  if ((TSFlags & (SIInstrFlags::VALU | Enc)) !=
-      (SIInstrFlags::VALU | Enc))
-    return true;
-  // This is FLAT/MUBUF LDS DMA.
-
-  SMLoc S = getImmLoc(AMDGPUOperand::ImmTyLDS, Operands);
-  StringRef CStr(S.getPointer());
-  if (!CStr.startswith("lds")) {
-    // This is incorrectly selected LDS DMA version of a FLAT/MUBUF load
-    // opcode. And LDS version should have 'lds' modifier, but it follows
-    // optional operands so its absense is ignored by the matcher.
-    Error(IDLoc, "missing dst operand or lds modifier");
-    return false;
-  }
-
-  return true;
-}
-
 bool AMDGPUAsmParser::validateExeczVcczOperands(const OperandVector &Operands) {
   if (!isGFX11Plus())
     return true;
@@ -4688,10 +4636,6 @@ bool AMDGPUAsmParser::validateInstruction(const MCInst &Inst,
       "d16 modifier is not supported on this GPU");
     return false;
   }
-  if (!validateMIMGDim(Inst)) {
-    Error(IDLoc, "dim modifier is required on this GPU");
-    return false;
-  }
   if (!validateMIMGMSAA(Inst)) {
     Error(getImmLoc(AMDGPUOperand::ImmTyDim, Operands),
           "invalid dim; must be MSAA type");
@@ -4768,14 +4712,6 @@ bool AMDGPUAsmParser::validateInstruction(const MCInst &Inst,
     return false;
   }
 
-  if (!validateLdsDMA(SIInstrFlags::FLAT, Inst, Operands, IDLoc)) {
-    return false;
-  }
-
-  if (!validateLdsDMA(SIInstrFlags::MUBUF, Inst, Operands, IDLoc)) {
-    return false;
-  }
-
   return true;
 }