[PATCH] D137721: [AArch64] Optimize more memcmp when the result is tested for [in]equality with 0

[chenglin.bi via Phabricator via llvm-commits]

bcl5980 added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:8559
+  // All the non-leaf nodes must be OR.
+  if (N->getOpcode() != ISD::OR)
+    return false;
----------------
Do we need add one-use check for `or`? 
Or generate the depth of the node to determine the more than one use node can enable the opt or not?


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:8580
+  // Try to express conjunction "cmp 0 (or (xor A0 A1) (xor B0 B1))" as:
+  // cmp A0, A0; ccmp A0, B1, 0, eq; cmp inv(Cond) flag
+  if (VT.isScalarInteger() && (Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
----------------
`cmp A0, A1; ccmp B0, B1` ?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D137721/new/

https://reviews.llvm.org/D137721