[llvm] 0b01aeb - [RISCV] Support BSET/BCLR/BINV in hasAllWUsers.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-11-09T11:32:20-08:00
New Revision: 0b01aebf5e658f3a9c026b194e7d60c0aa7066de

URL: https://github.com/llvm/llvm-project/commit/0b01aebf5e658f3a9c026b194e7d60c0aa7066de
DIFF: https://github.com/llvm/llvm-project/commit/0b01aebf5e658f3a9c026b194e7d60c0aa7066de.diff

LOG: [RISCV] Support BSET/BCLR/BINV in hasAllWUsers.

These instructions set, clear, or invert a single bit. If their
users don't use the upper 32 bits, they don't use the upper 32 bits
of their input.

Additionally the second operand BSET/BCLR/BINV is a shift amount
which only uses 6 bits of the source.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D137452

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp b/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
index 632f09c9f72a..d2e23a172b01 100644
--- a/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
+++ b/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
@@ -139,6 +139,9 @@ static bool hasAllWUsers(const MachineInstr &OrigMI, MachineRegisterInfo &MRI) {
         break;
 
       case RISCV::SLL:
+      case RISCV::BSET:
+      case RISCV::BCLR:
+      case RISCV::BINV:
         // Operand 2 is the shift amount which uses 6 bits.
         if (OpIdx == 2)
           break;
@@ -199,6 +202,9 @@ static bool hasAllWUsers(const MachineInstr &OrigMI, MachineRegisterInfo &MRI) {
       case RISCV::SH2ADD:
       case RISCV::SH3ADD:
       case RISCV::XNOR:
+      case RISCV::BSETI:
+      case RISCV::BCLRI:
+      case RISCV::BINVI:
         Worklist.push_back(UserMI);
         break;
       }