[llvm] 902976a - [RISCV] Support shift/rotate amount operands in isAllUsesReadW.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-11-09T11:32:20-08:00
New Revision: 902976a379c437de844601341a6329236932d19e

URL: https://github.com/llvm/llvm-project/commit/902976a379c437de844601341a6329236932d19e
DIFF: https://github.com/llvm/llvm-project/commit/902976a379c437de844601341a6329236932d19e.diff

LOG: [RISCV] Support shift/rotate amount operands in isAllUsesReadW.

These operands use 6 bits.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D137450

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp b/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
index 60302a98b791..632f09c9f72a 100644
--- a/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
+++ b/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
@@ -138,6 +138,22 @@ static bool hasAllWUsers(const MachineInstr &OrigMI, MachineRegisterInfo &MRI) {
         Worklist.push_back(UserMI);
         break;
 
+      case RISCV::SLL:
+        // Operand 2 is the shift amount which uses 6 bits.
+        if (OpIdx == 2)
+          break;
+        Worklist.push_back(UserMI);
+        break;
+
+      case RISCV::SRA:
+      case RISCV::SRL:
+      case RISCV::ROL:
+      case RISCV::ROR:
+        // Operand 2 is the shift amount which uses 6 bits.
+        if (OpIdx == 2)
+          break;
+        return false;
+
       case RISCV::ADD_UW:
       case RISCV::SH1ADD_UW:
       case RISCV::SH2ADD_UW:
@@ -171,7 +187,6 @@ static bool hasAllWUsers(const MachineInstr &OrigMI, MachineRegisterInfo &MRI) {
       case RISCV::AND:
       case RISCV::MUL:
       case RISCV::OR:
-      case RISCV::SLL:
       case RISCV::SUB:
       case RISCV::XOR:
       case RISCV::XORI: