[PATCH] D134711: [AArch64] Select SMULL for zero extended vectors when top bit is zero

Zain Jaffal via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Nov 8 06:03:32 PST 2022

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zjaffal added a comment.

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Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134711/new/

https://reviews.llvm.org/D134711

Previous message: [PATCH] D135991: [AArch64] Fix cost model for `udiv` instruction when one of the operands is a uniform constant
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