[PATCH] D124195: [AMDGPU] Separate out SGPR spills to VGPR lanes during PEI

[Christudasan Devadasan via Phabricator via llvm-commits]

cdevadas added inline comments.


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Comment at: llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll:415
 ; FLATSCR: s_add_i32 s32, s32, -12
-; GCN-NEXT:     v_readlane_b32 s33, [[CSR_VGPR]], 2
+; GCN-NEXT: s_mov_b32 s33, vcc_lo
 ; GCN-NEXT: s_or_saveexec_b64 [[COPY_EXEC1:s\[[0-9]+:[0-9]+\]]], -1{{$}}
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arsenm wrote:
> Why the behavior change? Is this restored in a later patch?
It's already been discussed. Jay earlier asked about the same in this review.
I'm planning a follow-up patch to regain it. Using the VRM map, the unused lanes of the last allocated VGPR virtual register for SGPR spilling can be tracked and can use later during FrameLowering while trying to spill FP/BP.


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124195/new/

https://reviews.llvm.org/D124195