[PATCH] D124195: [AMDGPU] Separate out SGPR spills to VGPR lanes during PEI

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll:415
 ; FLATSCR: s_add_i32 s32, s32, -12
-; GCN-NEXT:     v_readlane_b32 s33, [[CSR_VGPR]], 2
+; GCN-NEXT: s_mov_b32 s33, vcc_lo
 ; GCN-NEXT: s_or_saveexec_b64 [[COPY_EXEC1:s\[[0-9]+:[0-9]+\]]], -1{{$}}
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Why the behavior change? Is this restored in a later patch?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124195/new/

https://reviews.llvm.org/D124195