[PATCH] D136525: [M68k] Add codegen pattern for atomic load / store

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0x59616e added a comment.

Thanks for all of your edifying comments. The path is getting clearer. Here is my understanding. Correct me if I'm wrong.

1. `__atomic_*` is allowed to use lock, whilst `__sync_*` is lock-free.
2. We cannot use `__atomic_*` simultaneously with native atomic instruction or `__sync_*` because the lock may not be respected (i.e. race condition may occur).
3. `atomic_compare_and_swap` needs to be transformed to `__atomic_*` if we don't have `CAS` support.

Conclusion 1: According to 1 & 2 & 3,  if we don't have `CAS` support, we have to transform the `atomic_load` / `atomic_store` to `__atomic_*` library calls, instead of normal `load` / `store`, to avoid the mixture of lock-free instruction & non-lock-free library calls.

Conslusion 2: According to 1 & 2 & 3, If we have `CAS` support, we can just simply lower `atomic_load` / `atomic_store` / `atomic_compare_and_swap` to the native instruction, and expand the `atomic_rmw` to either `atomic_compare_and_swap` or `__sync_*` calls --- which all of them are lock-free.

Right ?


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https://reviews.llvm.org/D136525