[PATCH] D136525: [M68k] Add codegen pattern for atomic load / store

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

>> So I cannot lower atomic_load / atomic_store to native instruction whilst lower atomic_compare_and_swap to library call --- all of them should either be lowered to native instruction or library calls ?
>> Why the atomic width is not a property of a specific instruction ?
>
> To my best understanding, LLVM makes the decision to segregate native atomic supports by size, rather than a specific instruction, simply because most architectures do that. You either have full or no atomic support for a certain size. Meaning, m68k, as an anomaly, needs to do some extra works on this matter, which is not difficult because I believe the workflow I put at the beginning of this comment can lower atomic load / store to native instructions (on supported sub architectures) while lowering other atomic operations to libcalls for a given size.

The `__atomic_*` libcalls are allowed to be implemented using a lock.  If you try to mix in lock-free load and store operations, they won't respect that lock.

If m68k has `__sync_*` in libgcc, those are lock-free; you can use them alongside plain load/store instructions.

https://llvm.org/docs/Atomics.html has more details on various forms of calls.


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  https://reviews.llvm.org/D136525/new/

https://reviews.llvm.org/D136525