[PATCH] D136525: [M68k] Add codegen pattern for atomic load / store

[Min-Yih Hsu via Phabricator via llvm-commits]

myhsu added a comment.

In D136525#3901614 <https://reviews.llvm.org/D136525#3901614>, @0x59616e wrote:

> Thanks for all of your edifying comments. The path is getting clearer. Here is my understanding. Correct me if I'm wrong.
>
> 1. `__atomic_*` is allowed to use lock, whilst `__sync_*` is lock-free.
> 2. Non-lock-free function is NOT allowed to use simultaneously with the lock-free instruction or function, otherwise the lock may not be respected (i.e. race condition may occur)
> 3. `atomic_compare_and_swap` needs to be transformed to `__atomic_*` if we don't have `CAS` support.

I think we can also transform atomic_compare_and_swap to its `__sync` counterpart, `__sync_val_compare_and_swap`, if we don't have `CAS` (i.e. < M68020). And I think `__sync` is preferable here because it makes more sense to conditionally lower cmpxchg to libcall based on target CPU in the backend , compared to detecting target CPU in an IR Pass.


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