[PATCH] D136525: [M68k] Add codegen pattern for atomic load / store

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

The atomic width is never a property of a specific instruction.  Either *all* atomic ops of a given width are lock-free, or *all* atomic ops of a given width need to be transformed into `__atomic_*` libcalls.

So the right thing to do is something like the following, in M68kTargetLowering::M68kTargetLowering():

  if (Subtarget.atLeastM68020())
    setMaxAtomicSizeInBitsSupported(32);
  else
    setMaxAtomicSizeInBitsSupported(0);

If you need to emulate rmw ops on top of cmpxchg, implementing shouldExpandAtomicRMWInIR will tell AtomicExpandPass to handle that expansion for you.

It's possible to emulate a lock-free atomic cmpxchg on a uniprocessor, for example, https://www.kernel.org/doc/Documentation/arm/kernel_user_helpers.txt .  But the compiler can't do it itself; it needs some sort of operating system assistance.  And as far as I know, Linux requires an 68020 anyway, so I don't see a reason for you to go down that path.


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  https://reviews.llvm.org/D136525/new/

https://reviews.llvm.org/D136525