[PATCH] D136525: [M68k] Add codegen pattern for atomic load / store

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0x59616e added a comment.

In D136525#3899548 <https://reviews.llvm.org/D136525#3899548>, @efriedma wrote:

> The atomic width is never a property of a specific instruction.  Either *all* atomic ops of a given width are lock-free, or *all* atomic ops of a given width need to be transformed into `__atomic_*` libcalls.

I have a few questions:

- So I cannot lower `atomic_load` / `atomic_store` to native instruction whilst lower `atomic_compare_and_swap` to library call --- all of them should either be lowered to native instruction or library calls ?

- Why the atomic width is not a property of a specific instruction ?

Thanks !



================
Comment at: llvm/lib/Target/M68k/M68kTargetMachine.cpp:161
 
+void M68kPassConfig::addIRPasses() { addPass(createAtomicExpandPass()); }
+
----------------
RKSimon wrote:
> 0x59616e wrote:
> > RKSimon wrote:
> > > 0x59616e wrote:
> > > > RKSimon wrote:
> > > > > Also - do we need to add an pipeline.ll test file?
> > > > What is pipeline.ll ?
> > > https://github.com/llvm/llvm-project/blob/main/llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
> > > https://github.com/llvm/llvm-project/blob/main/llvm/test/CodeGen/ARM/O3-pipeline.ll
> > > https://github.com/llvm/llvm-project/blob/main/llvm/test/CodeGen/X86/opt-pipeline.ll
> > > 
> > > Different backends do it differently, but basically its a test file that checks what passes have been run at all/some opt levels
> > Thanks. This looks interesting. As far as I'm concerned, there is no reason not to add this one in M68k.
> So do we need to add TargetPassConfig::addIRPasses() to this call now?
Oh, I forgot it. I will address this later. Thanks !


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