[PATCH] D136678: [AArch64][SVE2] Add the SVE2.1 pext and ptrue predicate-as-counter instructions

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64RegisterInfo.td:917
+                            # RegClass # "RegClassID>";
+  let DiagnosticType = "InvalidSME" # name # "Reg";
+  let ParserMethod   = "tryParseSVEPredicateAsCounter";
----------------
InvalidSVE?


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Comment at: llvm/lib/Target/AArch64/AArch64RegisterInfo.td:921-938
+class PNRP8to15RegOp<string Suffix, AsmOperandClass C, int EltSize, RegisterClass RC>
+    : PPRRegOp<Suffix, C, ElementSizeNone, RC> {
+  let PrintMethod   = "printPredicateAsCounter<" # EltSize # ">";
+  let EncoderMethod = "EncodePPR_p8to15";
+  let DecoderMethod = "DecodePPR_p8to15RegisterClass";
+}
+
----------------
Not sure how good of a suggestion this is but can a predicate-as-counter register be anything other than p8-p15? If no then what about dropping all the `_p8to15` from these? We've got the PPR_p8to15 RegisterClass which is required, but all the other instances makes the code look a bit messy.


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Comment at: llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp:1203
 
+  template <unsigned Class> bool isSMEVectorReg() const {
+    RegKind RK;
----------------
`isSVEPredicateReg()`?


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Comment at: llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp:2598-2605
+      .Case("pn0", AArch64::P0)
+      .Case("pn1", AArch64::P1)
+      .Case("pn2", AArch64::P2)
+      .Case("pn3", AArch64::P3)
+      .Case("pn4", AArch64::P4)
+      .Case("pn5", AArch64::P5)
+      .Case("pn6", AArch64::P6)
----------------
Can these ever be hit? or does it help with diagnostics or something?


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  https://reviews.llvm.org/D136678/new/

https://reviews.llvm.org/D136678