[PATCH] D136678: [AArch64][SVE2] Add the SVE2.1 pext and ptrue predicate-as-counter instructions

[David Sherwood via Phabricator via llvm-commits]

david-arm added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64RegisterInfo.td:921-938
+class PNRP8to15RegOp<string Suffix, AsmOperandClass C, int EltSize, RegisterClass RC>
+    : PPRRegOp<Suffix, C, ElementSizeNone, RC> {
+  let PrintMethod   = "printPredicateAsCounter<" # EltSize # ">";
+  let EncoderMethod = "EncodePPR_p8to15";
+  let DecoderMethod = "DecodePPR_p8to15RegisterClass";
+}
+
----------------
paulwalker-arm wrote:
> Not sure how good of a suggestion this is but can a predicate-as-counter register be anything other than p8-p15? If no then what about dropping all the `_p8to15` from these? We've got the PPR_p8to15 RegisterClass which is required, but all the other instances makes the code look a bit messy.
I think cntp takes a predicate-as-counter in the full range 0-15. See D136747


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  https://reviews.llvm.org/D136678/new/

https://reviews.llvm.org/D136678