[PATCH] D124192: [AMDGPU] Callee must always spill writelane VGPRs

[Nicolai Hähnle via Phabricator via llvm-commits]

nhaehnle accepted this revision.
nhaehnle added a comment.
This revision is now accepted and ready to land.

We had a detailed offline discussion. The scan for v_writelane_b32/v_readlane_b32 is a (bad) heuristic for which **physical** VGPRs are used in a WWM fashion, so that a corresponding prolog spill / epilog reload is necessary. What we really should be doing is to remember this information when virtual registers are mapped to physical ones, which will involve calling `allocateWWMSpill` directly from the register allocator. I think that marking this as a TODO here, and then following up with a separate change that does the direct call of `allocateWWMSpill` from register allocation is a decent plan.


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https://reviews.llvm.org/D124192